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參數資料
| 型號： | CH7012A-T |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Chrontel CH7012 TV Output Device |
| 中文描述： | 昆泰CH7012電視輸出設備 |
| 文件頁數： | 1/42頁 |
| 文件大小： | 551K |
| 代理商： | CH7012A-T |
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CHRONTEL
201-0000-042 Rev. 1.1, 9/29/2000
1
CH7012A
Chrontel CH7012 TV Output Device
Features
TV output supporting up to 1024x768 graphics
resolutions
Programmable digital interface supports RGB and
YCrCb
TrueScale
TM
rendering engine supports underscan in
all TV output resolutions
Enhanced text sharpness and adaptive flicker
removal with up to 7 lines of filtering
Support for all NTSC and PAL formats
Provides CVBS, S-Video and SCART (RGB) outputs
TV connection detect
Programmable power management
10-bit video DAC outputs
Fully programmable through serial port
Complete Windows and DOS driver support
Low voltage interface support to graphics device
Offered in a 64-pin LQFP package
General Description
The CH7012 is a display controller device which
accepts a digital graphics input signal, and encodes and
transmits data to a TV output (analog composite, s-
video or RGB). The device accepts data over one 12-bit
wide variable voltage data port which supports five
different data formats including RGB and YCrCb.
The TV-Out processor will perform non-interlace to
interlace conversion with scaling and flicker filters, and
encode the data into any of the NTSC or PAL video
standards. The scaling and flicker filter is adaptive and
programmable to enable superior text display. Eight
graphics resolutions are supported up to 1024 by 768
with full vertical and horizontal underscan capability in
all modes. A high accuracy low jitter phase locked loop
is integrated to create outstanding video quality.
Support is provided for RGB bypass mode which
enables driving a VGA CRT with the input data.
Figure 1: Functional Block Diagram
PLL
RGB-YUV
CONVERTER
SYSTEM CLOCK
YUV-RGB CONVERTER
DIGITAL
INPUT
INTERFACE
SERIAL PORT REGISTER &
CONTROL BLOCK
LINE
MEMORY
TRUE SCALE
SCALING &
DEFLICKERING
ENGINE
TIMING & SYNC
GENERATOR
NTSC/PAL
ENCODER
& FILTERS
D [11:0]
PIXEL DATA
XCLK/XCLK*
H
V
XI/FIN
XO
P-OUT
SC
SD
RESET*
BCO
ISET
CSYNC
GPIO[1:0]
Y/R
CVBS/B
C/G
CVBS
Four
10-bit
DAC’s
相關PDF資料 |
PDF描述 |
|---|---|
| CH7202 | MPEG to TV Encoder with 8-bit Input |
| CH7203 | MPEG to TV Encoder with 16-bit Input |
| CH7203-V | MPEG to TV Encoder with 16-bit Input |
| CH7301A | Chrontel CH7301 DVI Output Device |
| CH7301A-T | Chrontel CH7301 DVI Output Device |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CH7013A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013A-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013A-V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013B-D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
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