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參數資料
| 型號： | CY28317ZC-2T |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | GIGATRUE 550 CAT6 MOLDED COMPONENT, RED 10FT |
| 中文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 6 X 12 MM, TSSOP-48 |
| 文件頁數： | 1/21頁 |
| 文件大小： | 172K |
| 代理商： | CY28317ZC-2T |
FTG for Mobile VIA PL133T and PLE133T Chipsets
CY28317-2
Cypress Semiconductor Corporation
Document #: 38-07094 Rev. *B
3901 North First Street
San Jose
CA 95134
Revised December 26, 2002
408-943-2600
17-2
Features
Single-chip system frequency synthesizer for mobile
VIA PL133T and PLE133T chipsets
Programmable clock output frequency with less than
1 MHz increment
Integrated fail-safe Watchdog Timer for system
recovery
Automatic switch to HW-selected or SW-programmed
clock frequency when Watchdog Timer time-out occurs
System RESET generation capability after a Watchdog
Timer time-out occurs or a change in output frequency
via SMBus interface
Support SMBus byte Read/Write and block Read/ Write
operations to simplify system BIOS development
Vendor ID and Revision ID support
Programmable drive strength for SDRAM and PCI
output clocks
Programmable output skew for CPU, PCI and SDRAM
Maximized EMI Suppression using Cypress’s Spread
Spectrum technology
Available in 48-pin SSOP and TSSOP packages
Key Specifications
CPU to CPU Output Skew:..........................................175 ps
PCI to PCI Output Skew:.............................................500 ps
Block Diagram
Pin Configuration
Note:
1.
Signals marked with
‘
*
’
have internal pull-up resistors.
[1]
VDD_REF
REF0
REF1/FS2*
PCI0_F/FS4*
PCI1/FS3*
OSC
PLL Ref Freq
PLL 1
X2
X1
VDD_PCI
PCI2:6
48MHz/FS0*
VDD_SDRAM
PLL2
÷
2,3,4
VTT_PWRGD#
PCI_STOP#
CPU_STOP#
VDD_48MHz
SMBus
Logic
SDATA
SCLK
SDRAM0:6
SDRAMIN
7
CPU0:1, CPUT, CPUC
÷
2
GND_CPU
*FS2/REF1
REF0
VTT_PWRGD#
GND_REF
X1
X2
VDD_PCI
*FS4/PCI0_F
*FS3/PCI1
GND_PCI
PCI2
PCI3
PCI4
PCI5
PCI6
SDRAMIN
*CPU_STOP#
*PCI_STOP#
*PD#
*MULT_SEL
GND_48MHz
SDATA
C
CPU0
CPU1
VDD_CPU_2.5
VDD_CPU_3.3
CPUT
CPUC
GND_CPU
RST#
IREF
SDRAM6
GND_SDRAM
SDRAM0
SDRAM1
VDD_SDRAM
SDRAM2
SDRAM3
GND_SDRAM
SDRAM4
SDRAM5
VDD_SDRAM
VDD_48MHz
48MHz/FS0*
24_48MHz/FS1*
SCLK
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Logic
Reset
RST#
IREF
MULT_SEL
PD#
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