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參數資料
| 型號： | CY7C1302V25 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 9-Mb Pipelined SRAM with QDR Architecture(帶QDR結構的9-M位流水線式 SRAM) |
| 中文描述： | 9 - MB的流水線架構的SRAM與國防評估報告（帶國防評估報告結構的9米位流水線式的SRAM） |
| 文件頁數： | 1/23頁 |
| 文件大小： | 252K |
| 代理商： | CY7C1302V25 |
Advanced Information
9-Mb Pipelined SRAM with QDR Architecture
Functional Description
CY7C1302V25
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
February 15, 2000
408-943-2600
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Features
Separate Independent Read and Write Data Ports
—Supports concurrent transactions
167-MHz Clock for High Bandwidth
—2.5 ns Clock-to-Valid access time
2-Word Burst on all accesses
Double Data Rate (DDR) interfaces on both Read &
Write Ports (data transferred at 333 MHz) @167 MHz
Two input clocks (K and K) for precise DDR timing
—SRAM uses rising edges only
Two output clocks (C and C) accounts for clock skew
and flight time mis-matches
Single multiplexed address input bus latches address
inputs for both READ and WRITE ports
Separate Port Selects for depth expansion
Synchronous internally self-timed writes
2.5V core power supply with HSTL Inputs and Outputs
13x15 mm - 1.0 mm pitch FBGA package, 165 ball (11x15
matrix)
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4V-1.9V)
JTAG Interface
Variable Impedance HSTL
The CY7C1302V25 is a 2.5V Synchronous-Pipelined SRAM
equipped with QDR architecture. QDR architecture consists
of two separate ports to access the memory array. The Read
port has dedicated Data Outputs to support Read operations
and the Write Port has dedicated Data inputs to support Write
operations. Access to each port is accomplished through a
common address bus. The Read address is latched on the
rising edge of the K clock and the Write address is latched on
the rising edge of K clock. QDR has separate data inputs and
data outputs to completely eliminate the need to “turn-around”
the data bus required with common I/O devices. Accesses to
the CY7C1302V25 Read and Write ports are completely inde-
pendent of one another. All accesses are initiated synchro-
nously on the rising edge of the positive input clock (K). In
order to maximize data throughput, both Read and Write ports
are equipped with Double Data Rate (DDR) interfaces. There-
fore, data can be transferred into the device on every rising
edge of both input clocks (K and K) and out of the device on
every rising edge of the output clock (C and C) thereby maxi-
mizing performance while simplifying system design.
Depth expansion is accomplished with a Port Select input for
each port. Each Port Selects allow each port to operate inde-
pendently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Logic Block Diagram
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Selection Guide
7C1302V25-167
7C1302V25-133
7C1302V25-100
Maximum Operating Frequency (MHz)
167
133
100
Maximum Operating Current (mA)
550
450
330
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C1302V25-167BZC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 2.5V 9M-Bit 512K x 18 2.5ns 165-Pin FBGA |
| CY7C1303BV25-167BZC | 功能描述:靜態隨機存取存儲器 1Mx18 2.5V QDR 靜態隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1303BV25-167BZCES | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 2.5V 18MBIT 1MX18 2.5NS 165FBGA - Bulk |
| CY7C1303TV25-167BZC | 功能描述:靜態隨機存取存儲器 NV靜態隨機存取存儲器 167 MHz 2.5V RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1303V25-133BZC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 2.5V 18MBIT 1MX18 3NS 165FBGA - Trays |
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