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參數(shù)資料
| 型號(hào)： | CY7C1427AV18 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 36-Mbit DDR-II SRAM 2-Word Burst Architecture(2字Burst結(jié)構(gòu)，36-Mbit DDR-II SRAM) |
| 中文描述： | 36兆位的DDR - II SRAM的2字突發(fā)架構(gòu)（2字突發(fā)結(jié)構(gòu),36 -兆位的DDR - II SRAM的） |
| 文件頁(yè)數(shù)： | 1/28頁(yè) |
| 文件大小： | 450K |
| 代理商： | CY7C1427AV18 |
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36-Mbit DDR-II SRAM 2-Word
Burst Architecture
CY7C1416AV18
CY7C1427AV18
CY7C1418AV18
CY7C1420AV18
Cypress Semiconductor Corporation
Document Number: 38-05616 Rev. *D
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised September 25, 2006
Features
36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)
300-MHz clock for high bandwidth
2-Word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces
(data transferred at 600 MHz) @ 300 MHz
Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches
Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
Synchronous internally self-timed writes
1.8V core power supply with HSTL inputs and outputs
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4V–V
DD
)
Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
Offered in both in lead-free and non lead-free packages
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1416AV18 – 4M x 8
CY7C1427AV18 – 4M x 9
CY7C1418AV18 – 2M x 18
CY7C1420AV18 – 1M x 36
Functional Description
The CY7C1416AV18, CY7C1427AV18, CY7C1418AV18 and
CY7C1420AV18 are 1.8V Synchronous Pipelined SRAM
equipped with DDR-II architecture. The DDR-II consists of an
SRAM core with advanced synchronous peripheral circuitry
and a 1-bit burst counter. Addresses for Read and Write are
latched on alternate rising edges of the input (K) clock. Write
data is registered on the rising edges of both K and K. Read
data is driven on the rising edges of C and C if provided, or on
the rising edge of K and K if C/C are not provided. Each
address location is associated with two 8-bit words in the case
of CY7C1416AV18 and two 9-bit words in the case of
CY7C1427AV18 that burst sequentially into or out of the
device. The burst counter always starts with a “0” internally in
the case of CY7C1416AV18 and CY7C1427AV18. On
CY7C1418AV18 and CY7C1420AV18, the burst counter takes
in the least significant bit of the external address and bursts
two 18-bit words in the case of CY7C1418AV18 and two 36-bit
words in the case of CY7C1420AV18 sequentially into or out
of the device.
Asynchronous inputs include output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the
two output echo clocks CQ/CQ, eliminating the need for
separately capturing data from each individual DDR SRAM in
the system design. Output data clocks (C/C) enable maximum
system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
300 MHz
300
825
278 MHz
278
775
250 MHz
250
700
200 MHz
200
600
167 MHz
167
500
Unit
MHz
mA
Maximum Operating Frequency
Maximum Operating Current
相關(guān)PDF資料 |
PDF描述 |
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| CY7C1441AV33 | 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM(36-Mb (1M x 36/2M x 18/512K x 72)流通式SRAM) |
| CY7C1443AV33 | 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM(36-Mb (1M x 36/2M x 18/512K x 72)流通式SRAM) |
| CY7C1447AV33 | 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM(36-Mb (1M x 36/2M x 18/512K x 72)流通式SRAM) |
| CY7C1444AV33 | 36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM(36-Mb (1M x 36/2M x 18)管道式DCD同步SRAM) |
| CY7C1445AV33 | 36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM(36-Mb (1M x 36/2M x 18)管道式DCD同步SRAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1431 WAF | 制造商:Cypress Semiconductor 功能描述: |
| CY7C143-55JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1440AV25-167BZXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 36MB (1Mx36) 2.5v 167MHz Sync 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1440AV25-250BZXI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 36MB (1Mx36) 2.5v 250MHz Sync 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1440AV25-250BZXIT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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