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參數(shù)資料
| 型號(hào)： | CY7C371I-110JI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | UltraLogic 32-Macrocell Flash CPLD |
| 中文描述： | FLASH PLD, 10 ns, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 214K |
| 代理商： | CY7C371I-110JI |
USE ULTRA37000 FOR
ALL NEW DESIGNS
UltraLogic 32-Macrocell Flash CPLD
CY7C371i
Cypress Semiconductor Corporation
Document #: 38-03032 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised April 19, 2004
Features
32 macrocells in two logic blocks
32 I/O pins
Five dedicated inputs including two clock pins
In-System Reprogrammable (ISR) Flash technology
—
JTAG interface
Bus Hold capabilities on all I/Os and dedicated inputs
No hidden delays
High speed
—
f
MAX
= 143 MHz
—
t
PD
= 8.5 n3s
—
t
S
= 5 ns
—
t
CO
= 6 ns
Fully PCI-compliant
3.3V or 5.0V I/O operation
Available in 44-pin PLCC, and TQFP packages
Pin-compatible with the CY7C372i
Functional Description
The CY7C371i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
F
LASH
370i family of high-density, high-speed CPLDs. Like
all members of the F
LASH
370i family, the CY7C371i is
designed to bring the ease of use and high performance of the
22V10, as well as PCI Local Bus Specification support, to
high-density CPLDs.
Like all of the UltraLogic F
LASH
370i devices, the CY7C371i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows, thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins. The ISR interface is enabled
using the programming voltage pin (ISR
EN
). Additionally,
because of the superior routability of the F
LASH
370i devices,
ISR often allows users to change existing logic designs while
simultaneously fixing pinout assignments.
The 32 macrocells in the CY7C371i are divided between two
logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
The logic blocks in the F
LASH
370i architecture are connected
with an extremely fast and predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings
flexibility, routability, speed, and a uniform delay to the inter-
connect.
Like all members of the F
LASH
370i family, the CY7C371i is rich
in I/O resources. Each macrocell in the device features an
associated I/O pin, resulting in 32 I/O pins on the CY7C371i.
In addition, there are three dedicated inputs and two
input/clock pins.
Selection Guide
7C371i-143 7C371i-110 7C371i-83 7C371iL-83 7C371i-66 7C371iL-66
8.5
10
12
5
6
8
6
6.5
8
75
75
75
Unit
ns
ns
ns
mA
Maximum Propagation Delay
[1]
, t
PD
Minimum Set-up, t
S
Maximum Clock to Output
[1]
, t
CO
Typical Supply Current, I
CC
Comm./Ind.
Note:
1. The 3.3V I/O mode timing adder, t
3.3IO
, must be added to this specification when V
CCIO
= 3.3V.
12
8
8
45
15
10
10
75
15
10
10
45
PIM
3
INPUT
MACROCELLS
2
Clock
Inputs
Inputs
LOGIC
BLOCK
A
LOGIC
BLOCK
B
2
2
36
16
16
36
16 I/Os
16 I/Os
16
16
INPUT/CLOCK
MACROCELLS
I/O
0
–I/O
15
I/O
16
–I/O
31
Logic Block Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C372I | UltraLogic 64-Macrocell Flash CPLD |
| CY7C373 | UltraLogic⑩ 64-Macrocell Flash CPLD |
| CY7C373I | UltraLogic⑩ 64-Macrocell Flash CPLD |
| CY7C375I | UltraLogic 128-Macrocell Flash CPLD |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C371I-66AC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 800 Gates 32 Macro Cells 66.6MHz CMOS Technology 5V 44-Pin TQFP 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 800 Gates 32 Macro Cells 66.6MHz 5V 44-Pin TQFP |
| CY7C371I-66JC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C371I-83JC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 800 Gates 32 Macro Cells 83.3MHz CMOS Technology 5V 44-Pin PLCC |
| CY7C371IL-66AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C371U66JC | 制造商:CYPRESS 功能描述:New |
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