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參數(shù)資料
| 型號(hào)： | DC1370A-L |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 8/34頁 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO 25MSPS LTC2256-12 |
| 軟件下載： | QuikEval II System |
| 設(shè)計(jì)資源： | DC1370A Design Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
| 相關(guān)產(chǎn)品： | DC718C-ND - DEMO QUIKEVAL-II DATA |
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LTC2258-12
LTC2257-12/LTC2256-12
16
225812fd
For more information www.linear.com/LTC2258-12
pin FuncTions
FULL-RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OVDD)
D0 to D11 (Pins 19-24, 29-34): Digital Outputs. D11 is
the MSB.
CLKOUT– (Pin 27): Inverted version of CLKOUT+.
CLKOUT+ (Pin 28): Data Output Clock. The digital outputs
normally transition at the same time as the falling edge
of CLKOUT+. The phase of CLKOUT+ can also be delayed
relative to the digital outputs by programming the mode
control registers.
DNC (Pins 17, 18, 35): Do not connect these pins.
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overflow or underflow has occurred.
DOUBLE DATA RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OVDD)
D0_1 to D10_11 (Pins 20, 22, 24, 30, 32, 34): Double
Data Rate Digital Outputs. Two data bits are multiplexed
onto each output pin. The even data bits (D0, D2, D4, D6,
D8, D10) appear when CLKOUT+ is low. The odd data bits
(D1, D3, D5, D7, D9, D11) appear when CLKOUT+ is high.
CLKOUT– (Pin 27): Inverted version of CLKOUT+.
CLKOUT+ (Pin 28): Data Output Clock. The digital outputs
normally transition at the same time as the falling and ris-
ing edges of CLKOUT+. The phase of CLKOUT+ can also
be delayed relative to the digital outputs by programming
the mode control registers.
DNC (Pins 17, 18, 19, 21, 23, 29, 31, 33, 35): Do not
connect these pins.
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overflow or underflow has occurred.
DOUBLE DATA RATE LVDS OUTPUT MODE
All Pins Below Have LVDS Output Levels. The Output
Current Level is Programmable. There is an Optional
Internal 100 Termination Resistor Between the Pins
of Each LVDS Output Pair.
D0_1–/D0_1+ to D10_11–/D10_11+ (Pins 19/20, 21/22,
23/24, 29/30, 31/32, 33/34): Double Data Rate Digital
Outputs.Twodatabitsaremultiplexedontoeachdifferential
output pair. The even data bits (D0, D2, D4, D6, D8, D10)
appear when CLKOUT+ is low. The odd data bits (D1, D3,
D5, D7, D9, D11) appear when CLKOUT+ is high.
CLKOUT–/CLKOUT+ (Pins 27/28): Data Output Clock.
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT+. The phase of
CLKOUT+ can also be delayed relative to the digital outputs
by programming the mode control registers.
OF–/OF+ (Pins 35/36): Over/Under Flow Digital Output.
OF+ is high when an overflow or underflow has occurred.
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