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參數(shù)資料
| 型號： | DDX4100A |
| 文件頁數(shù)： | 22/27頁 |
| 文件大小： | 1737K |
| 代理商： | DDX4100A |
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DDX-4100
BIT
D0
R/W
R/W
RST
0
NAME
DESCRIPTION
AC97_FC_Mode
AC’97 Full Compliant Mode (0 to enable). When in
FC mode any read of registers will return only valid
bits: bits marked as ‘reserved’ by AC’97 v2.0
specification will return 0, regardless of the RAM
contents.
Enable Double Buffer mode for the I
2
S input
interface (write 1 to enable this option). This is
recommended
ONLY
if this interface is operated in
SYNC mode (SRC bypassed).
DDX Gain setting (LSb/MSb). These two bits will
set the DDX stage gain and the compression as
shown in Table 4.
D1
R/W
0
I2SI_DBUFF_Mode
D2
R/W
0
DDX_Gain_0
D3
R/W
0
DDX_Gain_1
D4
R/W
1
DDX_Rst
DDX Reset (active high)
D5
R/W
1
DDX_ZD_Enable
DDX Zero Detect Feature. If this bit is 1 the
feature is enabled.
DDX Power Mode. (1 = Fixed for DDX-2060).
D6
R/W
1
DDX_PwrMode
D7
R/W
0
PLL_Factor
PLL factor (x2 or x8). It should be used according
to the input frequency provided to the device: 1
(x8) when 6.144MHz is provided, 0 (x2) when
24.576MHz is provided.
PLL Bypass. Setting this bit to 0 will bypass the
PLL; internal master clock will be directly
connected to XTI pin.
MCKOut Mode: 12.288 MHz (1) or 24.576MHz (0).
D8
R/W
1
PLL_Bypass
D9
R/W
0
MCKOUT_Mode
D10
R/W
0
I2S_SPDIF_Sel
I
2
S – S/PDIF Selector. Select the input source: set
to 0 for I
2
S input, 1 for S/PDIF input.
S/PDIF Mode. Set to 0 to select Analog mode, 1
to select Digital mode.
Sample Rate threshold (LSb/MSb). These bits are
used to select the threshold frequency enabling the
SRC anti-alias filter.
Table 5 shows the threshold selections.
D11
R/W
0
SPDIF_Mode
D12
R/W
1
SRC_THR_0
D13
R/W
0
SRC_THR_1
D14
R/W
0
DRLL_dbg
DRLL Debug Mode. This bit is used for a test
mode. Set to 0 for normal operation.
D15
R/W
0
SRC_Bypass
SRC Bypass. Setting this bit to 1 the SRC block
can be bypassed and the selected input I/F is
directly connected to the DSP.
Note: In TEST_MODE – PLL_Bypass = 0
Table 4 DDX Gain
DDX_GAIN_0
0
0
1
1
DDX_GAIN_1
0
1
0
1
DDX Gain
1x
2x
2x
3x
DDX Compression
NO
NO
YES
YES
22
Details and Specifications are subject to change without notice
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DDX4100ERRATA | DDX4100 Errata January 17 2002 |
| DDY-EJE-T2 | LED Colored Resin |
| DDY-EJE-T2U-1 | LED Colored Resin |
| DDY-EJE-U1 | LED Colored Resin |
| DDY-EJE-U2 | LED Colored Resin |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DDX-50P-K87 | 制造商:ITT Interconnect Solutions 功能描述:DDX-50P-K87 / 121551-1664 / D Sub |
| DDX-50S-0L2-A197-146 | 制造商:ITT Interconnect Solutions 功能描述:DDX-50S-0L2-A197-146 / 121551-0013 / D SUB |
| DDX-50S-A191-A197 | 制造商:ITT Interconnect Solutions 功能描述:DDX-50S-A191-A197 / 121551-1804 / D Sub |
| DDX8000-TRAY | 制造商:APOGEE TECHNOLOGY 功能描述:DDX 8 Channel Damped Ternary Controller |
| DDX8001-13TR | 制造商:APOGEE TECHNOLOGY 功能描述:DDX 8 Channel Damped Ternary Controller |
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