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參數資料
| 型號： | DDX4100A |
| 文件頁數： | 9/27頁 |
| 文件大?。?/td> | 1737K |
| 代理商： | DDX4100A |
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DDX-4100
6.0 DAP INPUT STAGE
The device provides three mutually exclusive input interfaces: I
2
S, S/PDIF and AC’97. Their
configuration is shown in Figure 4.
LFE
CENTE
S
SL/CENTER
LEFT
RIGHT
LF
CENTE
SR
SL/CENTER
LEFT
RIGHT
YRA
YRAM
I2C
LRCK
MCK
PLL_Bypass
PLL_Factor
PLL
XTI
CK_OUT
/2 or /8
/1024
I2S_SPDIF_Sel
S/PDIF
I2S
AC97
AC97_Sel
SRC_Bypass
LRCK
SRC
DSP
I2S
DDX
Figure 4: DAP Input Stage
6.1
Using this input interface a maximum of 4 channels can be sent to the DSP. This I/F can be configured
as either master or slave. When the master the sampling frequency is fixed to 48 kHz, the SRC can be
by passed using the
SRC_Bypass
configuration bit. If slave operation is selected the full range between
32kHz and 96kHz is supported but the SRC must always be in the processing path (no bypass). In order
to select this interface the AC97_Mode pin must be tied to GND and the I2S_SPDIF_Sel must be 0.
The DDX-4100 includes a double-buffering feature to adapt the phase of the incoming serial data to the
internal data frame. Double-buffering is enabled by setting Bit D1 in the Configuration Register A,
address 0x5B. Enabling this function requires that the incoming data rate is exactly equal to the internal
data rate, e.g. for a synchronous application using an ADC. If the nominal data input frequency and the
internal data frequency are not exactly the same, this function will not properly work and samples will be
lost causing performance degradation. It is not recommended to use this feature when the SRC is
enabled.
Input Rate : | L0 | R0 | L1 | R1 | L2 | R2 | ...
Output Rate : | | | L0 | R0 | L1 | R1 | L2 | R2 | ...
6.2
Input from S/PDIF
This interface is compliant with the AES/EBU IEC 958, S/PDIF and EIA CP-340/1201 professional and
consumer standards. The full range from 32 kHz up to 96 kHz is supported but the SRC bypass option
must be switched off. Using the
SPDIF_Mode
bit this interface can be configured as a digital or an
analog input. If the analog mode is selected the line receiver can decode differential as well as single
Input from I
2
S
9
Details and Specifications are subject to change without notice
相關PDF資料 |
PDF描述 |
|---|---|
| DDX4100ERRATA | DDX4100 Errata January 17 2002 |
| DDY-EJE-T2 | LED Colored Resin |
| DDY-EJE-T2U-1 | LED Colored Resin |
| DDY-EJE-U1 | LED Colored Resin |
| DDY-EJE-U2 | LED Colored Resin |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DDX-50P-K87 | 制造商:ITT Interconnect Solutions 功能描述:DDX-50P-K87 / 121551-1664 / D Sub |
| DDX-50S-0L2-A197-146 | 制造商:ITT Interconnect Solutions 功能描述:DDX-50S-0L2-A197-146 / 121551-0013 / D SUB |
| DDX-50S-A191-A197 | 制造商:ITT Interconnect Solutions 功能描述:DDX-50S-A191-A197 / 121551-1804 / D Sub |
| DDX8000-TRAY | 制造商:APOGEE TECHNOLOGY 功能描述:DDX 8 Channel Damped Ternary Controller |
| DDX8001-13TR | 制造商:APOGEE TECHNOLOGY 功能描述:DDX 8 Channel Damped Ternary Controller |
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