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參數(shù)資料
| 型號： | DDX4100ERRATA |
| 英文描述： | DDX4100 Errata January 17 2002 |
| 中文描述： | DDX4100勘誤表02年1月17日 |
| 文件頁數(shù)： | 17/27頁 |
| 文件大小： | 1737K |
| 代理商： | DDX4100ERRATA |
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DDX-4100
11.1.4 Data Input
During the data input the DDX-4100 samples the SDA signal on the rising edge of clock SCL. For correct
device operation the SDA signal must be stable during the rising edge of the clock and the data can
change only when the SCL line is low.
11.2 DEVICE ADDRESSING
To start communication between the master and the DDX-4100, the master must initiate with a start
condition. Following this, the master sends onto the SDA line 8-bits (MSB first) corresponding to the
device select address and read or write mode.
The 7 most significant bits are the device address identifiers, corresponding to the I
2
C bus definition. In
the DDX-4100 the I
C interface has two device addresses depending on the SA pin configuration,
0011110 when SA = 0, and 0011111 when SA = 1.
The 8
th
bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0 for write
mode. After a START condition the DDX-4100 identifies on the bus the device address and if a match is
found, it acknowledges the identification on SDA bus during the 9
bit time. The byte following the device
identification byte is the internal space address.
11.3
WRITE OPERATION (see fig. 16)
Following the START condition the master sends a device select code with the RW bit set to 0. The
DDX-4100 acknowledges this and the writes for the byte of internal address. After receiving the internal
byte address the DDX-4100 again responds with an acknowledgement.
11.3.1 Byte Write
In the byte write mode the master sends one data byte, this is acknowledged by the DDX-4100. The
master then terminates the transfer by generating a STOP condition.
11.3.2 Multi-byte Write
The multi-byte write modes can start from any internal address. The master generating a STOP condition
terminates the transfer.
Write Mode Sequence
DEV-ADDR
ACK
START
RW
SUB-ADDR
ACK
DATA IN
ACK
STOP
BYTE
WRITE
DEV-ADDR
ACK
START
RW
SUB-ADDR
ACK
DATA IN
ACK
STOP
MULTIBYTE
WRITE
DATA IN
ACK
17
Details and Specifications are subject to change without notice
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