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參數資料
| 型號： | DDX4100ERRATA |
| 英文描述： | DDX4100 Errata January 17 2002 |
| 中文描述： | DDX4100勘誤表02年1月17日 |
| 文件頁數： | 18/27頁 |
| 文件大小： | 1737K |
| 代理商： | DDX4100ERRATA |
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DDX-4100
Figure 10 Read Mode Sequence
DEV-ADDR
ACK
START
RW
DATA
NO ACK
STOP
CURRENT
ADDRESS
READ
DEV-ADDR
ACK
START
RW
SUB-ADDR
ACK
DEV-ADDR
ACK
STOP
RANDOM
ADDRESS
READ
DATA
NO ACK
START
RW
DEV-ADDR
ACK
START
DATA
ACK
DATA
ACK
STOP
SEQUENTIAL
CURRENT
READ
DATA
NO ACK
DEV-ADDR
ACK
START
RW
SUB-ADDR
ACK
DEV-ADDR
ACK
SEQUENTIAL
RANDOM
READ
DATA
ACK
START
RW
DATA
ACK
NO ACK
STOP
DATA
RW=
HIGH
12.0
REGISTER SUMMARY
12.1
Reset Register (address 00h)
D15
0
D14 D13 D12 D11 D10
0
0
0
D9
0
D8
0
D7
1
D6
1
D5
1
D4
0
D3
0
D2
1
D1
0
D0
0
0
0
Writing any value to this register performs a register reset, which causes all registers to revert to their
default values. Reading this register returns 00E4h as it is the ID code of the part and it’s 3D Stereo
Enhancement type (see AC’97 revision 2.1 specification, section 6.3.1).
12.2
LR Volume Register (address 02h)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Mute
ML6
ML5
ML4
ML3
ML2
ML1
ML0
X
MR6
MR5
MR4
MR4
MR2
MR1
MR0
This register manages the stereo (both right and left channels) output signal volume. The MSB of the
register is the mute bit. ML6 through ML0 set the left channel level, MR6 though MR0 set the right
channel. There are two options: ‘Full Compliance’ operating mode (bit D0 in the CRA register, address
5Ah, is set to ‘0’) only 6 bits are active (Mx0 to Mx5) and each step corresponds to 1.5dB. In ‘Proprietary”
mode (bit D1 in the CRA register is set to ‘1’), Mx0 to Mx6 can have the values between 0h to 68h (110
1000) and each step corresponds to 1dB. Greater values are undefined.
The default value is 8000h (1000 0000 0000 0000), which corresponds to 0dB attenuation.
‘Full Compliance Mode’
Mute
Mx6 – Mx0
0
X00 0000
0
X01 1111
0
X11 1111
1
xxx xxxx
Function
0 dB Attenuation
46.5dB Attenuation
94.5dB Attenuation
∞
dB Attenuation
18
Details and Specifications are subject to change without notice
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