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| 型號： | DDX4100ERRATA |
| 英文描述： | DDX4100 Errata January 17 2002 |
| 中文描述： | DDX4100勘誤表02年1月17日 |
| 文件頁數(shù)： | 23/27頁 |
| 文件大小： | 1737K |
| 代理商： | DDX4100ERRATA |
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DDX-4100
DDX Gain Compression
Since a full-scale output of the GC/Vol block is mapped to full output modulation, any signal exceeding
0dBFS at the output of the GC/Vol block will clip. The purpose of the compression algorithm is to reduce
the gain of the system when 0dBFS has been exceeded. This eliminates clipping, thus performing an
output limiting function. This yields constant output once the gained input exceeds 0dBFS.
With DDX_GAIN_0 set to 1, the output of the GC/Vol block is compared to a threshold set just below
0dBFS. When the GC/Vol exceeds this threshold the system gain is reduced following a set time constant
at a set gain reduction rate. The gain reduction is stored as a variable. If the subsequent output of GC/Vol
remains below a lower threshold for a set time, the gain is increased following another set time, at a set
gain rate. Thus, seven constants determine the attack, release and limiting characteristics of the
compression algorithm. These constants have been tuned for the lowest perceived audio distortion when
reducing the dynamic range of a recording due to 0dBFS being exceeded.
OUTPUT
GAIN/VOLUME
INPUT
+
SATURATION
ATTENUATION
GAIN
RMS
LIMITER
Figure 12 Gain Limiter
Table 5 SRC Threshold
SRC_THR_0
SRC_THR_1
0
1
0
1
Threshold Frequency
INACTIVE
58.875 to 61.125kHz
78.973 to 81.000kHz
Always active
0
0
1
1
12.10 Configuration Register B (CRB) (address 5Ch)
D15
D14
D13
D12
D11
I2SO_
MSbLSb
LRCK_
Master
Pol
Master
_Pol
D10
I2SO_
Align
_2
D9
I2SO_
Align
_1
D8
I2SO_
Align
_0
D7
I2SI_
MSbLSb
D6
I2SI_
LRCK
_Master
D5
I2SI_
LRCL
_Pol
D4
I2SI_
BCK
_Master
D3
I2SI_
BICK
_Pol
D2
I2SI_
Align
_2
D1
I2SI_
Align
_1
D0
I2SI_
Align
_0
I2SO_
I2SO_
LRCK_
I2SO_
BCK_
I2SO_
BICK
23
Details and Specifications are subject to change without notice
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