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參數資料
| 型號： | DJIXE972MHEA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發器 |
| 文件頁數： | 46/92頁 |
| 文件大小： | 666K |
| 代理商： | DJIXE972MHEA4 |
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Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
46
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
5.7.3.1
Physical Coding Sublayer
The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/
decoding function.
For 100BASE-TX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver
as long as TX_EN is de-asserted.
5.7.3.1.1
Preamble Handling
When the MAC asserts TX_EN, the PCS substitutes a /J/K symbol pair, also known as the Start-of-
Stream Delimiter (SSD), for the first two nibbles received across the MII. The PCS layer continues
to encode the remaining MII data, following the 4B/5B coding in
Table 15
, until TX_EN is de-
asserted. It then returns to supplying IDLE symbols to the line driver.
In the receive direction, the PCS layer performs the opposite function, substituting two preamble
nibbles for the SSD. In 100 Mbps operation, preamble is always passed through the PCS layer to
the MII interface.
Table 15. 4B/5B Coding (Sheet 1 of 2)
Code Type
4B Code
3 2 1 0
Name
5B Code
4 3 2 1 0
Interpretation
DATA
0 0 0 0
0
1 1 1 1 0
Data 0
0 0 0 1
1
0 1 0 0 1
Data 1
0 0 1 0
2
1 0 1 0 0
Data 2
0 0 1 1
3
1 0 1 0 1
Data 3
0 1 0 0
4
0 1 0 1 0
Data 4
0 1 0 1
5
0 1 0 1 1
Data 5
0 1 1 0
6
0 1 1 1 0
Data 6
0 1 1 1
7
0 1 1 1 1
Data 7
1 0 0 0
8
1 0 0 1 0
Data 8
1 0 0 1
9
1 0 0 1 1
Data 9
1 0 1 0
A
1 0 1 1 0
Data A
1 0 1 1
B
1 0 1 1 1
Data B
1 1 0 0
C
1 1 0 1 0
Data C
1 1 0 1
D
1 1 0 1 1
Data D
1 1 1 0
E
1 1 1 0 0
Data E
1 1 1 1
F
1 1 1 0 1
Data F
IDLE
undefined
I
1
1 1 1 11
Used as inter-stream fill code
1. The /I/ (Idle) code group is sent continuously between frames.
2. The /J/ and /K/ (SSD) code groups are always sent in pairs, and /K/ follows /J/.
3. The /T/ and /R/ (ESD) code groups are always sent in pairs, and /R/ follows /T/.
4. An /H/ (Error) code group is used to signal an error condition.
相關PDF資料 |
PDF描述 |
|---|---|
| DJIXE972MKAA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MKCA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MKEA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MLAA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MLCA4 | Single-Port 10/100 Mbps PHY Transceiver |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DJIXE972MKAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MKCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MKEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MLAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MLCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
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