- 您現在的位置：買賣IC網 > PDF目錄376726 > DJIXF972MTAA4 (Intel Corp.) Single-Port 10/100 Mbps PHY Transceiver PDF資料下載
參數資料
| 型號： | DJIXF972MTAA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發器 |
| 文件頁數： | 39/92頁 |
| 文件大小： | 666K |
| 代理商： | DJIXF972MTAA4 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁當前第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
39
5.6.4
Carrier Sense
Carrier Sense (CRS) is an asynchronous output.
CRS is always generated when the LXT972M Transceiver receives a packet from the line.
CRS is also generated when the LXT972M Transceiver is in half-duplex mode when a packet
is transmitted.
Table 14
summarizes the conditions for assertion of carrier sense, data loopback, and collision
signals. Carrier sense is not generated when a packet is transmitted and in full-duplex mode.
5.6.5
Error Signals
When the LXT972M Transceiver is in 100 Mbps mode and receives an invalid symbol from the
network, it asserts RX_ER and drives “0101” on the RXD pins.
The TX_ER function that forces ‘H’ symbols out on the TPOP/TPON twisted pair is not
implemented in the LXT972M Transceiver.
5.6.6
Collision
The LXT972M Transceiver asserts its collision signal asynchronously to any clock whenever the
line state is half-duplex and the transmitter and receiver are active at the same time.
Table 14
summarizes the conditions for assertion of carrier sense, data loopback, and collision signals.
Table 14. Carrier Sense, Loopback, and Collision Conditions
Speed
Duplex Condition
Carrier Sense
Test
Loop-
back
1, 2
Operational
Loop-
back
1, 2
Collision
100
Mbps
Full-Duplex
Receive Only
Yes
No
None
Half-Duplex
Transmit or Receive
No
No
Transmit and Receive
10
Mbps
Full-Duplex
Receive Only
Yes
No
None
Half-Duplex,
Register bit 16.8 = 0
Transmit or Receive
Yes
Yes
Transmit and Receive
Half-Duplex,
Register bit 16.8 = 1
Transmit or Receive
No
No
Transmit and Receive
1. Test Loopback is enabled when Register bit 0.14 = 1.
2. For descriptions of Test Loopback and Operational Loopback, see
Section 5.6.7, “Loopback” on page 40
.
相關PDF資料 |
PDF描述 |
|---|---|
| DJIXF972MTCA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MTEA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MBAA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MBCA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MBEA4 | Single-Port 10/100 Mbps PHY Transceiver |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DJIXF972MTCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MTEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXFEAD0QE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFEAD0QE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFEAD0SE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
發布緊急采購，3分鐘左右您將得到回復。