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參數資料
| 型號： | DJIXF972MTAA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發器 |
| 文件頁數： | 82/92頁 |
| 文件大?。?/td> | 666K |
| 代理商： | DJIXF972MTAA4 |
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Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
82
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
Table 48
lists auto-negotiation next page transmit bits.
Table 49
lists auto-negotiation link partner next page receive bits.
Table 48. Auto-Negotiation Next Page Transmit Register - Address 7, Hex 7
Bit
Name
Description
Type
1
Default
7.15
Next Page (NP)
0 = Last page
1 = Additional next pages follow
R/W
0
7.14
Reserved
Ignore when read.
RO
0
7.13
Message Page
(MP)
0 = Register bits 7.10:0 are user defined.
1 = Register bits 7.10.0 follow IEEE message page
format.
R/W
1
7.12
Acknowledge 2
(ACK2)
0 = Cannot comply with message
1 = Complies with message
R/W
0
7.11
Toggle (T)
0 = Previous value of the transmitted Link Code Word
equalled logic one
1 = Previous value of the transmitted Link Code Word
equalled logic zero
R/W
0
7.10:0
Message/
Unformatted
Code Field
If Register bits 7.13 = 0, Register bits 7.10:0 are user-
defined.
If Register bits 7.13 = 1, Register bits 7.10:0 follow
IEEE message page format.
R/W
00000000
001
1. RO = Read Only. R/W = Read/Write
Table 49. Auto-Negotiation Link Partner Next Page Receive Register - Address 8, Hex 8
Bit
Name
Description
Type
1
Default
8.15
Next Page (NP)
0 = Link Partner has no additional next pages to
send
1 = Link Partner has additional next pages to send
RO
0
8.14
Acknowledge (ACK)
0 = Link Partner has not received Link Code Word
from LXT972M Transceiver.
1 = Link Partner has received Link Code Word from
LXT972M Transceiver.
RO
0
8.13
Message Page (MP)
0 = Register bits 8.10:0 are user defined.
1 = Register bits 8.10:0 follow IEEE message page
format.
RO
0
8.12
Acknowledge 2
(ACK2)
0 = Link Partner cannot comply with the message
1 = Link Partner complies with the message
RO
0
8.11
Toggle (T)
0 = Previous value of transmitted Link Code Word
equal to logic one
1 = Previous value of transmitted Link Code Word
equal to logic zero
RO
0
8.10:0
Message/Unformatted
Code Field
If Register bit 8.13 = 0, Register bits 18.10:0 are
user defined.
If Register bit 8.13 = 1, Register bits 18.10:0 follow
IEEE message page format.
RO
000000
0000
1. RO = Read Only.
相關PDF資料 |
PDF描述 |
|---|---|
| DJIXF972MTCA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MTEA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MBAA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MBCA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MBEA4 | Single-Port 10/100 Mbps PHY Transceiver |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DJIXF972MTCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MTEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXFEAD0QE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFEAD0QE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFEAD0SE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
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