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參數資料
| 型號： | DSPIC33FJ16MC304T-I/PT |
| 廠商： | Microchip Technology |
| 文件頁數： | 44/76頁 |
| 文件大小： | 0K |
| 描述： | IC DSPIC MCU/DSP 16K 44TQFP |
| 產品培訓模塊： | Asynchronous Stimulus |
| 標準包裝： | 1,200 |
| 系列： | dsPIC™ 33F |
| 核心處理器： | dsPIC |
| 芯體尺寸： | 16-位 |
| 速度： | 40 MIP |
| 連通性： | I²C，IrDA，LIN，SPI，UART/USART |
| 外圍設備： | 欠壓檢測/復位，DMA，電機控制 PWM，QEI，POR，PWM，WDT |
| 輸入/輸出數： | 35 |
| 程序存儲器容量： | 16KB（16K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數據轉換器： | A/D 9x10b/12b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-TQFP |
| 包裝： | 帶卷 (TR) |
| 配用： | DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32 |
| 其它名稱： | DSPIC33FJ16MC304T-I/PTTR |
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2007-2012 Microchip Technology Inc.
DS70283K-page 49
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
4.6.3
MODULO ADDRESSING
APPLICABILITY
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W
register. Address boundaries check for addresses
equal to:
The upper boundary addresses for incrementing
buffers
The lower boundary addresses for decrementing
buffers
It is important to realize that the address boundaries
check for addresses less than or greater than the upper
(for incrementing buffers) and lower (for decrementing
buffers) boundary addresses (not just equal to).
Address changes can, therefore, jump beyond
boundaries and still be adjusted correctly.
4.7
Bit-Reversed Addressing
Bit-Reversed Addressing mode is intended to simplify
data re-ordering for radix-2 FFT algorithms. It is
supported by the X AGU for data writes only.
The modifier, which can be a constant value or register
contents, is regarded as having its bit order reversed. The
address source and destination are kept in normal order.
Thus, the only operand requiring reversal is the modifier.
4.7.1
BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-Reversed Addressing mode is enabled in any of
these situations:
BWM bits (W register selection) in the MODCON
register are any value other than ‘15’ (the stack
cannot be accessed using Bit-Reversed
Addressing)
The BREN bit is set in the XBREV register
The addressing mode used is Register Indirect
with Pre-Increment or Post-Increment
If the length of a bit-reversed buffer is M = 2N bytes,
the last ‘N’ bits of the data buffer start address must
be zeros.
XB<14:0> is the Bit-Reversed Address modifier, or
‘pivot point’, which is typically a constant. In the case of
an FFT computation, its value is equal to half of the FFT
data buffer size.
When enabled, Bit-Reversed Addressing is executed
only for Register Indirect with Pre-Increment or
Post-Increment Addressing and word-sized data
writes. It will not function for any other addressing
mode or for byte-sized data, and normal addresses are
generated instead. When Bit-Reversed Addressing is
active, the W Address Pointer is always added to the
address modifier (XB), and the offset associated with
the Register Indirect Addressing mode is ignored. In
addition, as word-sized data is a requirement, the LSb
of the EA is ignored (and always clear).
If Bit-Reversed Addressing has already been enabled
by setting the BREN bit (XBREV<15>), a write to the
XBREV register should not be immediately followed by
an indirect read operation using the W register that has
been designated as the bit-reversed pointer.
Note:
The modulo corrected effective address is
written back to the register only when
Pre-Modify or Post-Modify Addressing
mode is used to compute the effective
address. When an address offset (such as
[W7 + W2]) is used, Modulo Address
correction is performed but the contents of
the register remain unchanged.
Note:
All bit-reversed EA calculations assume
word-sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
Note:
Modulo Addressing and Bit-Reversed
Addressing
should
not
be
enabled
together. If an application attempts to do
so, Bit-Reversed Addressing will assume
priority when active for the X WAGU and X
WAGU,
Modulo
Addressing
will
be
disabled. However, Modulo Addressing will
continue to function in the X RAGU.
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| dsPIC33FJ256GP506A-E/MR | 功能描述:數字信號處理器和控制器 - DSP, DSC 16 Bit MCU/DSP 64LD 40MIPS 256KB FLASH RoHS:否 制造商:Microchip Technology 核心:dsPIC 數據總線寬度:16 bit 程序存儲器大小:16 KB 數據 RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數量:35 定時器數量:3 設備每秒兆指令數:50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| dsPIC33FJ256GP506A-E/PT | 功能描述:數字信號處理器和控制器 - DSP, DSC 16Bit 40MIPS 256KB Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數據總線寬度:16 bit 程序存儲器大小:16 KB 數據 RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數量:35 定時器數量:3 設備每秒兆指令數:50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| DSPIC33FJ256GP506A-H/MR | 制造商:Microchip Technology Inc 功能描述:16 BIT MCU/DSP 64LD 40MIPS 256KB FLASH - Trays |
| DSPIC33FJ256GP506A-H/PT | 制造商:Microchip Technology Inc 功能描述:16 BIT MCU/DSP 64LD 40MIPS 256KB FLASH - Trays |
| dsPIC33FJ256GP506A-I/MR | 功能描述:數字信號處理器和控制器 - DSP, DSC 16 Bit MCU/DSP 64LD 40MIPS 256KB FLASH RoHS:否 制造商:Microchip Technology 核心:dsPIC 數據總線寬度:16 bit 程序存儲器大小:16 KB 數據 RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數量:35 定時器數量:3 設備每秒兆指令數:50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
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