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參數資料
| 型號： | EBD21RD4ADNA-7A |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks) |
| 中文描述： | 256M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封裝： | DIMM-184 |
| 文件頁數： | 1/19頁 |
| 文件大小： | 176K |
| 代理商： | EBD21RD4ADNA-7A |
Document No. E0433E10 (Ver. 1.0)
Date Published November 2003 (K) Japan
URL: http://www.elpida.com
Elpida Memory,Inc. 2003
PRELIMINARY DATA SHEET
2GB Registered DDR SDRAM DIMM
EBD21RD4ADNA
(256M words
×
72 bits, 2 Ranks)
Description
The EBD21RD4ADNA is a 256M words
×
72 bits, 2
ranks Double Data Rate (DDR) SDRAM Module,
mounting 36 pieces of DDR SDRAM sealed in TCP
package. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 2-bit prefetch-
pipelined architecture. Data strobe (DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. This module provides high density
mounting without utilizing surface mount technology.
Decoupling capacitors are mounted beside each TCP
on the module board.
Note: Do not push the cover or drop the modules in
order to avoid mechanical defects, which may
result in electrical defects.
Features
184-pin socket type dual in line memory module
(DIMM)
PCB height: 30.48mm
Lead pitch: 1.27mm
2.5V power supply
Data rate: 333Mbps/266Mbps (max.)
2.5 V (SSTL_2 compatible) I/O
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
Data inputs and outputs are synchronized with DQS
4 internal banks for concurrent operation
(Component)
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
referenced to both edges of DQS
Auto precharge option for each burst access
Programmable burst length: 2, 4, 8
Programmable /CAS latency (CL): 2, 2.5
Refresh cycles: (8192 refresh cycles /64ms)
7.8
μ
s maximum average periodic refresh interval
2 variations of refresh
Auto refresh
Self refresh
1 piece of PLL clock driver, 1 piece of register driver
and 1 piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD)
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相關代理商/技術參數 |
參數描述 |
|---|---|
| EBD21RD4ADNA-7A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks) |
| EBD21RD4ADNA-7B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks) |
| EBD21RD4ADNA-7B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks) |
| EBD21RD4ADNA-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks) |
| EBD24A | 制造商:ADAM-TECH 制造商全稱:Adam Technologies, Inc. 功能描述:EURO BLOCKS TS & EB SERIES |
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