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參數資料
| 型號： | EP4CE40F29I8LN |
| 廠商： | Altera |
| 文件頁數： | 18/42頁 |
| 文件大小： | 0K |
| 描述： | IC CYCLONE IV E FPGA 40K 780FBGA |
| 產品培訓模塊： | Designing an IP Surveillance Camera Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview |
| 特色產品： | Cyclone? IV FPGAs |
| 標準包裝： | 36 |
| 系列： | CYCLONE® IV E |
| LAB/CLB數： | 2475 |
| 邏輯元件/單元數： | 39600 |
| RAM 位總計： | 1161216 |
| 輸入/輸出數： | 532 |
| 電源電壓： | 0.97 V ~ 1.03 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 780-BBGA |
| 供應商設備封裝： | 780-FBGA（29x29） |
| 其它名稱： | 544-2684 |
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Chapter 1: Cyclone IV Device Datasheet
1–25
Switching Characteristics
December 2013
Altera Corporation
tDLOCK
Time required to lock dynamically (after switchover,
reconfiguring any non-post-scale counters/delays or
areset
is deasserted)
——
1
ms
tOUTJITTER_PERIOD_DEDCLK (6)
Dedicated clock output period jitter
FOUT 100 MHz
—
300
ps
FOUT < 100 MHz
—
30
mUI
tOUTJITTER_CCJ_DEDCLK (6)
Dedicated clock output cycle-to-cycle jitter
FOUT 100 MHz
—
300
ps
FOUT < 100 MHz
—
30
mUI
tOUTJITTER_PERIOD_IO (6)
Regular I/O period jitter
FOUT 100 MHz
—
650
ps
FOUT < 100 MHz
—
75
mUI
tOUTJITTER_CCJ_IO (6)
Regular I/O cycle-to-cycle jitter
FOUT 100 MHz
—
650
ps
FOUT < 100 MHz
—
75
mUI
tPLL_PSERR
Accuracy of PLL phase shift
—
±50
ps
tARESET
Minimum pulse width on areset signal.
10
—
ns
tCONFIGPLL
Time required to reconfigure scan chains for PLLs
—
3.5 (7)
—
SCANCLK
cycles
fSCANCLK
scanclk
frequency
—
100
MHz
tCASC_OUTJITTER_PERIOD_DEDCLK
Period jitter for dedicated clock output in cascaded
PLLs (FOUT 100 MHz)
—
425
ps
Period jitter for dedicated clock output in cascaded
PLLs (FOUT 100 MHz)
—
42.5
mUI
Notes to Table 1–25:
(1) This table is applicable for general purpose PLLs and multipurpose PLLs.
(2) You must connect VCCD_PLL to VCCINT through the decoupling capacitor and ferrite bead.
(3) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(4) The VCO frequency reported by the Quartus II software in the PLL Summary section of the compilation report takes into consideration the VCO
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
(5) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source that is less
than 200 ps.
(6) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL when an input jitter of 30 ps is applied.
(7) With 100-MHz scanclk frequency.
(8) The cascaded PLLs specification is applicable only with the following conditions:
■ Upstream PLL—0.59 MHz Upstream PLL bandwidth < 1 MHz
■ Downstream PLL—Downstream PLL bandwidth > 2 MHz
(9) PLL cascading is not supported for transceiver applications.
Table 1–25. PLL Specifications for Cyclone IV Devices (1), (2) (Part 2 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
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相關代理商/技術參數 |
參數描述 |
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| EP4CE40U19I7N | 功能描述:FPGA - 現場可編程門陣列 FPGA - Cyclone IV E 2475 LABs 328 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4CE55 | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV FPGA Device Family Overview |
| EP4CE55F17C8 | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV Device Datasheet |
| EP4CE55F23C6 | 功能描述:FPGA - 現場可編程門陣列 FPGA - Cyclone IV E 3491 LABs 324 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4CE55F23C6N | 功能描述:FPGA - 現場可編程門陣列 FPGA - Cyclone IV E 3491 LABs 324 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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