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參數資料
型號: EPF10K20RI208-4
廠商: Altera
文件頁數: 46/128頁
文件大小: 0K
描述: IC FLEX 10K FPGA 20K 208-RQFP
產品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
產品變化通告: Package Change 30/Jun/2010
標準包裝: 48
系列: FLEX-10K®
LAB/CLB數: 144
邏輯元件/單元數: 1152
RAM 位總計: 12288
輸入/輸出數: 147
門數: 63000
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 208-BFQFP 裸露焊盤
供應商設備封裝: 240-RQFP(32x32)
產品目錄頁面: 603 (CN2011-ZH PDF)
其它名稱: 544-2214
24
Altera Corporation
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Asynchronous Preset
An asynchronous preset is implemented as either an asynchronous load,
or with an asynchronous clear. If DATA3 is tied to VCC, asserting
LABCTRL1
asynchronously loads a one into the register. Alternatively, the
Altera software can provide preset control by using the clear and
inverting the input and output of the register. Inversion control is
available for the inputs to both LEs and IOEs. Therefore, if a register is
preset by only one of the two LABCTRL signals, the DATA3 input is not
needed and can be used for one of the LE operating modes.
Asynchronous Preset & Clear
When implementing asynchronous clear and preset, LABCTRL1 controls
the preset and LABCTRL2 controls the clear. DATA3 is tied to VCC,
therefore, asserting LABCTRL1 asynchronously loads a one into the
register, effectively presetting the register. Asserting LABCTRL2 clears the
register.
Asynchronous Load with Clear
When implementing an asynchronous load in conjunction with the clear,
LABCTRL1
implements the asynchronous load of DATA3 by controlling
the register preset and clear. LABCTRL2 implements the clear by
controlling the register clear; LABCTRL2 does not have to feed the preset
circuits.
Asynchronous Load with Preset
When implementing an asynchronous load in conjunction with preset, the
Altera software provides preset control by using the clear and inverting
the input and output of the register. Asserting LABCTRL2 presets the
register, while asserting LABCTRL1 loads the register. The Altera software
inverts the signal that drives DATA3 to account for the inversion of the
register’s output.
Asynchronous Load without Preset or Clear
When implementing an asynchronous load without preset or clear,
LABCTRL1
implements the asynchronous load of DATA3 by controlling
the register preset and clear.
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相關代理商/技術參數
參數描述
EPF10K20RI208-4N 功能描述:FPGA - 現場可編程門陣列 FPGA - Flex 10K 144 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K20RI240-4 功能描述:FPGA - 現場可編程門陣列 FPGA - Flex 10K 144 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K20RI240-4N 功能描述:FPGA - 現場可編程門陣列 FPGA - Flex 10K 144 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K20TC144-3 功能描述:FPGA - 現場可編程門陣列 FPGA - Flex 10K 144 LABs 102 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K20TC144-3N 功能描述:FPGA - 現場可編程門陣列 FPGA - Flex 10K 144 LABs 102 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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