欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數(shù)資料
型號(hào): EPF10K30ETC144-3
廠商: Altera
文件頁數(shù): 11/100頁
文件大小: 0K
描述: IC FLEX 10KE FPGA 30K 144-TQFP
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 180
系列: FLEX-10KE®
LAB/CLB數(shù): 216
邏輯元件/單元數(shù): 1728
RAM 位總計(jì): 24576
輸入/輸出數(shù): 102
門數(shù): 119000
電源電壓: 2.375 V ~ 2.625 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-TQFP(20x20)
其它名稱: 544-1267
18
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
The programmable flipflop in the LE can be configured for D, T, JK, or SR
operation. The clock, clear, and preset control signals on the flipflop can
be driven by global signals, general-purpose I/O pins, or any internal
logic. For combinatorial functions, the flipflop is bypassed and the output
of the LUT drives the output of the LE.
The LE has two outputs that drive the interconnect: one drives the local
interconnect and the other drives either the row or column FastTrack
Interconnect routing structure. The two outputs can be controlled
independently. For example, the LUT can drive one output while the
register drives the other output. This feature, called register packing, can
improve LE utilization because the register and the LUT can be used for
unrelated functions.
The FLEX 10KE architecture provides two types of dedicated high-speed
data paths that connect adjacent LEs without using local interconnect
paths: carry chains and cascade chains. The carry chain supports
high-speed counters and adders and the cascade chain implements
wide-input functions with minimum delay. Carry and cascade chains
connect all LEs in a LAB as well as all LABs in the same row. Intensive use
of carry and cascade chains can reduce routing flexibility. Therefore, the
use of these chains should be limited to speed-critical portions of a design.
Carry Chain
The carry chain provides a very fast (as low as 0.2 ns) carry-forward
function between LEs. The carry-in signal from a lower-order bit drives
forward into the higher-order bit via the carry chain, and feeds into both
the LUT and the next portion of the carry chain. This feature allows the
FLEX 10KE architecture to implement high-speed counters, adders, and
comparators of arbitrary width efficiently. Carry chain logic can be
created automatically by the Altera Compiler during design processing,
or manually by the designer during design entry. Parameterized functions
such as LPM and DesignWare functions automatically take advantage of
carry chains.
Carry chains longer than eight LEs are automatically implemented by
linking LABs together. For enhanced fitting, a long carry chain skips
alternate LABs in a row. A carry chain longer than one LAB skips either
from even-numbered LAB to even-numbered LAB, or from odd-
numbered LAB to odd-numbered LAB. For example, the last LE of the
first LAB in a row carries to the first LE of the third LAB in the row. The
carry chain does not cross the EAB at the middle of the row. For instance,
in the EPF10K50E device, the carry chain stops at the eighteenth LAB and
a new one begins at the nineteenth LAB.
相關(guān)PDF資料
PDF描述
VI-BNH-CX CONVERTER MOD DC/DC 52V 75W
RS1K DIODE GPP FAST 1A 800V SMA
VI-BNH-CW CONVERTER MOD DC/DC 52V 100W
EBM18DRKI CONN EDGECARD 36POS DIP .156 SLD
VI-BN3-CX CONVERTER MOD DC/DC 24V 75W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPF10K30ETC144-3DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EPF10K30ETI144-1DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EPF10K30ETI144-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 216 LABs 102 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K30ETI144-2DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EPF10K30ETI144-2N 制造商:Altera Corporation 功能描述:
主站蜘蛛池模板: 大姚县| 昌平区| 商河县| 商城县| 汝南县| 吉隆县| 宜宾县| 南宁市| 丹巴县| 尼勒克县| 黑山县| 临颍县| 镇江市| 广昌县| 山东| 旺苍县| 忻州市| 新龙县| 井陉县| 新安县| 抚顺县| 温州市| 灵山县| 通海县| 沙河市| 内丘县| 若羌县| 河津市| 怀安县| 南皮县| 丰镇市| 本溪| 新源县| 海原县| 蒲江县| 福贡县| 泸溪县| 葫芦岛市| 元氏县| 鄂州市| 莆田市|