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參數(shù)資料
| 型號： | F49L800BA-70T |
| 廠商： | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 8 Mbit (1M x 8/512K x 16) 3V Only CMOS Flash Memory |
| 中文描述： | 512K X 16 FLASH 3V PROM, 70 ns, PDSO48 |
| 封裝： | 12 X 20 MM, TSOP1-48 |
| 文件頁數(shù)： | 12/47頁 |
| 文件大小： | 435K |
| 代理商： | F49L800BA-70T |
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ES MT
F49L800UA/F49L800BA
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision: 1.2 12/47
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are all don’t
cares for this command.
The reset command may be written between the
sequence cycles in an erase command sequence
before erasing begins. This resets the device to reading
array data. Once erasure begins, however, the device
ignores reset commands until the operation is
complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the
sequence cycles in an auto-select command sequence.
Once in the auto-select mode, the reset command must
be written to return to reading array data (also applies
to auto-select during Erase Suspend).
If DQ5 goes high(see “DQ5: Exceeded Timing Limits”
section) during a program or erase operation, writing
the reset command returns the device to reading array
data (also applies during Erase Suspend).
Read Command
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or
Embedded Erase algorithm.
When the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The
system can read array data using the standard read
timings, except that if it reads an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again read
array data with the same exception. See “Erase
Suspend/Erase
Resume
information on this mode.
The system must issue the reset command to
re-enable the device for reading array data if DQ5 goes
high, or while in the auto-select mode. See the “Reset
Command” section. See also the “Read Mode” in the
“Device Operations” section for more information. Refer
to Figure 5 for the timing diagram.
Commands”
for
more
Program Command
The program command sequence programs one byte
into the device. Programming is a four-bus-cycle
operation. The program command sequence is initiated
by writing two unlock write cycles, followed by the
program set-up command. The program address and
data are written next, which in turn initiate the
Embedded Program algorithm. The system is not
required to provide further controls or timings. The
device automatically provides internally generated
program pulses and verifies the programmed cell
margin.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by using
DQ7, DQ6, or RY/
BY
. See “Write Operation Status”
section for more information on these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware
reset
immediately
programming operation. The Program command
sequence should be reinitiated once the device has
reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from a
“0” back to a “1”. Attempting to do so may halt the
operation and set DQ5 to “1”, or cause the Data Polling
algorithm to indicate the operation was successful.
However, a succeeding read will show that the data is
still “0”. Only erase operations can convert a “0” to a
“1”.
Chip Erase Command
terminates
the
Chip erase is a six-bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm.
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase.
Any commands written to the chip during the
Embedded Erase algorithm are ignored. Note that a
hardware reset during the chip erase operation
immediately terminates the operation. The Chip Erase
command sequence should be reinitiated once the
device has returned to reading array data, to ensure
the data integrity.
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| F50-A24-3002A90 | RF Coaxial Connectors |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| F49L800BA-70TG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:8 Mbit (1M x 8/512K x 16) 3V Only CMOS Flash Memory |
| F49L800BA-70TIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:8 Mbit (1M x 8/512K x 16) 3V Only CMOS Flash Memory |
| F49L800BA-90T | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:8 Mbit (1M x 8/512K x 16) 3V Only CMOS Flash Memory |
| F49L800BA-90TG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:8 Mbit (1M x 8/512K x 16) 3V Only CMOS Flash Memory |
| F49L800BA-90TIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:8 Mbit (1M x 8/512K x 16) 3V Only CMOS Flash Memory |
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