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參數(shù)資料
| 型號(hào)： | FAN5068MPX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | DDR-1/DDR-2 plus ACPI Regulator Combo |
| 中文描述： | 1.5 A SWITCHING CONTROLLER, 345 kHz SWITCHING FREQ-MAX, QCC24 |
| 封裝： | 5 X 5 MM, MO-220WHCC, MLP-24 |
| 文件頁數(shù)： | 9/18頁 |
| 文件大小： | 159K |
| 代理商： | FAN5068MPX |
FAN5068
PRODUCT SPECIFICATION
REV. 1.0.1 9/9/04
9
Regulator Sequencing
The VCC pin provides power to all logic and analog control
functions of the regulator including:
1.
2.
3.
4.
Power for the 3.3V regulator
LDRV gate driver current
HDRV boot diode charging current.
The regulator analog control and logic
This pin must be decoupled with a ceramic capacitor (4.7μF
or larger recommended) as close as possible to the VCC pin.
After VCC is above UVLO, the start-up sequence begins as
shown in Figure 6.
T1 to T3:
After initial power-up, the IC will ignore all logic
inputs for a time period (T3-T1) of about:
where T3-T1 is in ms if C
SS
is in nF. At T2 (about 2/3 of the
way from T1 to T3), the 3.3V-ALW LDO is in regulation.
The 3.3V LDO’s slew rate is limited by the discharge slope
of CSS. If 3.3V MAIN has come up prior to this time, the
3.3V-ALW node will already be pre-charged through the
body diode of Q5 (see Figure 1).
T3 to T4:
The IC will start VDDQ only if 5V MAIN is
above its UVLO threshold (5V MAIN OK). Provided 5V
MAIN is up before T3, the IC waits about 100μs before
initiating soft-start on VDDQ to allow CSS time to fully
discharge. The IC is in “SLEEP” or S5 state when EN is low.
In S5, only the 3.3V LDO is on. If the IC is in S5 at T4, CSS
will be held to 0V.
T4 to T5:
After VDDQ is stablized (when CSS is at about
1.3V) an internal VDDQ OK is generated which will allow
the 1.2V LDO and the VTT LDO to start. To ensure that the
VDDQ output is not subjected to large transient currents dur-
ing S3 to S0 transition, the VTT and 1.2V LDO slew rates
are limited by the slew rate of the SS cap until the LDO is in
regulation. In addition, the VTT regulator is current limited.
After VDDQ OK becomes true, CSS will be held to 1.2V
until S3#I goes high.
S0 to S3:
The system signals this transition by dropping the
S3#I signal. When this occurs, S3#O goes low, and the 3.3V
LDO turns on. The 1.2V LDO and the VTT LDO are turned
off, and CSS is discharged to 2V. SBSW pulls low to turn on
the P-Channel 5V DUAL switch.
S3 to S0:
The system signals this transition by raising the
S3#I signal. S0 mode is not entered until 5V MAIN OK.
Then the following occurs:
S3#O releases
SBSW pulls high to turn off the P-Channel switch
The 3.3V LDO turns off
The 1.2V LDO and the VTT LDO are turned on and, and
CSS is allowed to charge up
In most systems, the ATX power supply is enabled when
S3#I goes from high. At that point, 5V and 3.3V MAIN will
start to rise. The FAN5068 waits until 5V MAIN is above
4.5V to turn on Q3 and Q5. This can cause about a 10%
“bump” in both 5V DUAL and 3.3V ALW when Q3 and Q5
turn on, since at that point, 5V MAIN and 3.3V MAIN are at
90% of their regulation value.
Figure 4. S3 to S0 Transition: 5V DUAL
To eliminate the “bump”, add delay to the 5V MAIN pin as
shown below. The 5V MAIN pin on the FAN5068 does not
supply power to the IC, it is only used to monitor the voltage
level of the 5V MAIN supply, and therefore is a high imped-
ance input.
Figure 5. Adding Delay to 5V MAIN
Another method to eliminate the potential for this “bump” is
to use the PWR_OK to drive the 5V MAIN pin. Some sys-
tems cannot tolerate the long delay for PWR_OK (>100ms)
to assert, hence the solution in figure 5 may be preferrable.
S5 to S3:
During S5 to S3 transition, the IC will pull SBSW
low with a 500nA current sink to limit inrush in Q4 if 5V
MAIN is below its UVLO threshold. At that time, 5V DUAL
is discharged. The limited gate drive controls the inrush
current through Q4 as it charges C1 (capacitance on 5V
Dual). Depending on the C
GD
of Q4, the current available
from 5VSB, and the size of C1, C13 may be omitted.
If 5V MAIN is above its UVLO threshold, SBSW will be
pulled down with an impedance of about 2K. VDDQ will not
start until 5V MAIN OK is true.
T3
T1
–
6.4
---------5
C
×
=
(1)
S3#I
5V MAIN
4.5V
5V DUAL
5V Dual "bump"
S3#O
5V MAIN
4
+5MAIN
FROM
ATX
R
DLY
C
DLY
I
Q4(INRUSH)
C13
5
10
7
–
×
C
GD(Q4)
+
C1
=
(2)
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| FAN5068DDR | FAN5068 Component calculation and simulation tools |
| FAN5069MTCX | PWM and LDO Controller Combo |
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| FAN5069_08 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:PWM and LDO Controller Combo |
| FAN5069B_BAC3116B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
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