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參數(shù)資料
| 型號： | FAN5069 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | PWM and LDO Controller Combo |
| 中文描述： | PWM和LDO控制器組合 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 379K |
| 代理商： | FAN5069 |
11
www.fairchildsemi.com
FAN5069 Rev. 1.1.0
F
Oscillator Clock Frequency (PWM)
The clock frequency on the oscillator is set using an external
resistor, connected between R(T) pin and ground. The fre-
quency follows the graph as shown in Figure 18. The minimum
clock frequency is 200KHz which is when R(T) pin is left open.
Select the value of R(T) as shown in the equation below. This
equation is valid for all F
OSC
> 200kHz.
(EQ. 2)
Where F
OSC
is in Hz.
For example for F
OSC
= 300kHz, R(T) = 50K
Ω.
R
RAMP
Selection and Feed Forward Operation
The FAN5069 provides for feed forward function through R
RAMP
.
The value of R
RAMP
effectively changes the slope of the internal
ramp keeping the gain of the modulator constant for changes in
input voltage. R
RAMP
also affects the current limit as explained
in the later sections. The minimum value recommended to use
for R
RAMP
is 400K
Ω
at maximum input voltage of 24V. For other
input voltages (E.g. 8V), calculate R
RAMP
resistor using the fol-
lowing equation:
(EQ. 3)
Gate Drive Section
The adaptive gate control logic translates the internal PWM
control signal into the MOSFET gate drive signals and provides
necessary amplification, level shifting, and shoot-through pro-
tection. Also, it has functions that help optimize the IC perfor-
mance over a wide range of operating conditions. Since the
MOSFET switching time can vary dramatically from device to
device and with the input voltage, the gate control logic provides
adaptive dead time by monitoring the gate-to-source voltages of
both upper and lower MOSFETs. The lower MOSFET drive is
not turned on until the gate-to-source voltage of the upper MOS-
FET has decreased to less than approximately 1V. Similarly, the
upper MOSFET is not turned on until the gate-to-source voltage
of the lower MOSFET has decreased to less than approximately
1V. This allows a wide variety of upper and lower MOSFETs to
be used without a concern for simultaneous conduction, or
shoot-through.
A low impedance path between the driver pin and the MOSFET
gate is recommended for the adaptive dead-time circuit to work
properly. Any delay along this path reduces the delay generated
by the adaptive dead-time circuit thereby increasing the
chances for shoot-through.
Protection
In the FAN5069, the converter is protected against extreme over
load, short circuit, over voltage, and under voltage conditions.
All of these extreme conditions generate an internal “fault latch”
which shuts down the converter. For all fault conditions both the
high-side and the low-side drives are off except in the case of
OVP where the low-side MOSFET is turned on until the voltage
on the FB pin goes below 0.4V. The fault latch can be reset
either by toggling the EN pin or recycling VCC to the chip.
Over Current Limit (PWM)
The PWM converter is protected against overloading through a
cycle-by-cycle current limit set by selecting R
ILIM
resistor. An
internal 10μA current source sets the threshold voltage for the
output of the summing amplifier. When the summing amplifier
output exceeds this threshold level, the current limit comparator
trips and the PWM starts skipping pulses. If the current limit trip-
ping occurs for 16 continuous clock cycles, a fault latch is set
and the controller shuts down the converter. This shut down fea-
ture is disabled during the start-up until the voltage on the SS
capacitor crosses 1.2V.
To achieve current limit, the FAN5069 monitors the inductor cur-
rent during the OFF time by monitoring and holding the voltage
across the lower MOSFET. The voltage across the lower MOS-
FET is sensed between the PGND and the SW pins.
The output of the summing amplifier is a function of the inductor
current, R
DS_ON
of the bottom FET and the gain of the current
sense amplifier. With the R
DS_ON
method of current sensing,
the current limit can vary widely from unit to unit. R
DS_ON
not
only varies from unit to unit, but also has a typical junction tem-
perature coefficient of about 0.4%/°C (consult the MOSFET
datasheet for actual values). Hence, the set point of the actual
current limit decreases in proportion to increase in MOSFET die
temperature. A factor of 1.6 in the current limit set point typically
compensates for all MOSFET R
DS_ON
variations, assuming the
MOSFET's heat sinking will keep its operating die temperature
below 125°C.
For more accurate current limit setting, use resistor sensing. In
a resistor sensing scheme, an appropriate current sense resis-
tor is connected between the source terminal of the bottom
MOSFET and PGND.
Set the current limit by selecting R
ILIM
as follows:
(EQ. 4)
Where
R
ILIM
is in K
Ω,
I
MAX
is the maximum load current.
K1 is a constant to compensate for the variation of MOSFET
R
DS_ON
. Typically, this value is 1.6.
With K1=1.6, I
MAX
=10A, R
DS_ON
=7m
Ω
, V
IN
=24V, V
OUT
=1.5V,
F
SW
= 300KHz, and R
RAMP
=400K
Ω
, R
ILIM
equals 168.18 K
Ω
.
Auto Restart (PWM)
The FAN5069 supports two modes of response when the inter-
nal fault latch is set. The user can configure it to keep the power
supply latched in the OFF state OR in the Auto Restart mode.
When the EN pin is tied to V
CC
, the power supply is latched
OFF. When the EN pin is terminated with a 100nF to GND, the
power supply is in Auto Restart mode. The table below
describes the relationship between PWM restart and setting on
EN pin. Do not leave the EN pin open without any capacitor.
R T
9
200
F
OSC
10
3
×
–
(
)
----------------------------------------------------
Ω
=
R
RAMP
V
------------------------
1.8
–
55
10
6
–
×
=
EN Pin
PWM/Restart
Pull to GND
OFF
V
CC
No restart after fault
Cap to GND
Restart after
TDELAY (Sec.) =
Where C is in
μ
F
RILIM
128
--------------------------------------------------–
1
----------
–
-------------------------------------------------------
×
+
+
K
Ω
=
0.85
C
×
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