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參數資料
| 型號： | FAN5069 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | PWM and LDO Controller Combo |
| 中文描述： | PWM和LDO控制器組合 |
| 文件頁數： | 12/20頁 |
| 文件大小： | 379K |
| 代理商： | FAN5069 |
12
www.fairchildsemi.com
FAN5069 Rev. 1.1.0
F
The fault latch can also be reset by recycling the VCC to the
controller.
Under Voltage Protection (PWM)
The PWM converter output is monitored constantly for under
voltage at the FB pin. If the voltage on the FB pin stays lower
than 75% of internal Vref for 16 clock cycles, the fault latch is set
and the converter shuts down. This shutdown feature is dis-
abled during startup till the voltage on the SS capacitor reaches
1.2V.
Over Voltage Protection (PWM)
The PWM converter output voltage is monitored constantly at
the FB pin for over voltage. If the voltage on the FB pin stays
higher than 115% of internal Vref for 2 clock cycles, the control-
ler turns OFF the upper MOSFET and turns ON the lower MOS-
FET. This crowbar action stops when the voltage on the FB pin
comes down to 0.4V to prevent the output voltage from becom-
ing negative. This OVP protection feature is active as soon as
the voltage on the EN pin becomes high.
Turning ON the low-side MOSFETs on an OVP condition pulls
down the output resulting in a reverse current which starts to
build up in the inductor. If the output over-voltage is due to fail-
ure of the high-side MOSFET, this crowbar action pulls down the
input supply or blow its fuse, protecting the system which is very
critical.
During soft-start, if the output overshoots beyond 115% of Vref,
then the output voltage is brought down by the low-side MOS-
FET till the voltage on the FB pin goes below 0.4V. The fault
latch is NOT set until the voltage on the SS pin reaches 1.2V.
Once the fault latch is set, the converter shuts down.
Figure 21. Over Voltage Protection
Thermal Fault Protection
The FAN5069 features thermal protection where the IC temper-
ature is monitored. When the IC junction temperature exceeds
+160°C, the controller shuts down and when the junction tem-
perature gets down to +125°C, the converter restarts.
LDO Section
The LDO controller is designed to provide ultra low voltages, as
low as, 0.8V for GTL type of loads. The regulating loop employs
a very fast response feedback loop. Hence, small capacitors
can be used to keep track of the changing output voltage during
transients. For stable operation, the minimum capacitance on
the output needs to be 100μF and the typical ESR needs to be
around 100m
Ω
.
The maximum voltage at the gate drive for the MOSFET can
reach close to 0.5V below the VCC of the controller. For exam-
ple, for a 1.2V output, the minimum enhancement voltage
required with 4.75V on V
CC
is 3.05V (4.75V-0.5V-1.2V = 3.05V).
The drop-out voltage for the LDO is dependent on the load cur-
rent and the MOSFET chosen. It is recommended to use low
enhancement voltage MOSFETs for the LDO.
The soft-start on the LDO output (ramp) is controlled by the
capacitor on the SS pin to GND. The LDO output is enabled
only when the voltage on the SS pin reaches 2.2V. Refer to fig-
ure 9 for startup waveform.
Design Section
General Design Guidelines
Establishing the input voltage range and the maximum current
loading on the converter before choosing the switching fre-
quency and the inductor ripple current is highly recommended.
There are design tradeoffs in choosing an optimum switching
frequency and the ripple current.
The input voltage range should accommodate the worst-case
input voltage with which the converter may ever operate. This
voltage needs to account for the cable drop encountered from
the source to the converter. Typically, the converter efficiency
tends to be higher at lower input voltage conditions.
When selecting maximum loading conditions, consider the tran-
sient and steady state (continuous) loading separately. The
transient loading affects the selection of the inductor and the
output capacitors. Steady state loading affects the selection of
MOSFETs, input capacitors, and other critical heat generating
components.
The selection of switching frequency is tricky. While higher
switching frequency results in smaller components, it also
results in lower efficiency. Ideal selection of switching frequency
takes into account the maximum operating voltage. The MOS-
FET switching losses are directly proportional to F
SW
and the
square function of the input voltage.
When selecting the inductor, consider the min. and max. load
conditions. Lower inductor values produce better transient
response but result in higher ripple & lower efficiency due to
high RMS currents. Optimum minimum inductance value
enables the converter to operate at the boundary of continuous
and discontinuous conduction modes.
Setting the Output Voltage (PWM)
The internal reference for the PWM controller is at 0.8V. The
output voltage of the PWM regulator can be set in the range of
0.8V to 90% of its power input by an external resistor divider.
The output is divided down by an external voltage divider to the
FB pin (for example, R1 and R
BIAS
as in Figure 24.). Thus the
output voltage is given by the following equation:
(EQ. 5)
To minimize noise pickup on this node, keep the resistor to GND
(R
BIAS
) below 10K
Ω
.
Inductor Selection (PWM)
When the ripple current, switching frequency of the converter,
and the input-output voltages are established, select the induc-
tor using the following equation:
(EQ. 6)
S
R
Q
S
R
Q
FB
0.4V
115% Vref
ILIM
UV
V
SS
>1.2V
Delay
2 Clks
Fault
Latch
LS Drive
OV
EN
V
OUT
0.8V
1
BIAS
----------------
+
×
=
L
MIN
V
OUT
----------------------------------------------
SW
---------------
2
–
Ripple
=
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| FAN5069EMTCX | 功能描述:電流型 PWM 控制器 PWM and ULDO Controller Combo RoHS:否 制造商:Texas Instruments 開關頻率:27 KHz 上升時間: 下降時間: 工作電源電壓:6 V to 15 V 工作電源電流:1.5 mA 輸出端數量:1 最大工作溫度:+ 105 C 安裝風格:SMD/SMT 封裝 / 箱體:TSSOP-14 |
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