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參數資料
型號: FAN9611MX
廠商: Fairchild Semiconductor
文件頁數: 20/35頁
文件大小: 1556K
描述: IC PFC CTLR DUAL BCM 16-SOIC
標準包裝: 1
系列: Sync-Lock™
模式: 臨界傳導(BCM)
頻率 - 開關: 16.5kHz ~ 525kHz
電流 - 啟動: 80µA
電源電壓: 9 V ~ 18 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 16-SOIC
包裝: 標準包裝
其它名稱: FAN9611MXFSDKR
 
?2008 Fairchild Semiconductor Corporation
 
www.fairchildsemi.com
FAN9611 " Rev. 1.1.7
20
under-voltage lockout), which gradually discharges
the compensation capacitor. As the output voltage
decreases, the FB pin falls, pulling LOW the SS
capacitor voltage. Similarly to the shutdown, once
the VIN pin is released, operation resumes after
several milliseconds of delay needed to determine
that   the   input   voltage   is   above   the   turn-on
threshold. At least one line cycle peak must be
detected   above   the   turn-on   threshold   before
operation can resume at the following line voltage
zero-crossing. The converter starts following normal
soft-start procedure.
6.   Layout and Connection Guidelines
For high-power applications, two or more PCB layers
are recommended to effectively use the ground pattern
to minimize the switching noise interference.
The FAN9611 incorporates fast-reacting input circuits,
short propagation delays, and strong output stages
capable   of   delivering   current   peaks   over   1.5 A   to
facilitate fast voltage transition times. Many high-speed
power circuits can be susceptible to noise injected from
their own output or external sources, possibly causing
output re-triggering. These effects can be especially
obvious if the circuit is tested in breadboard or non-
optimal circuit layouts with long input or output leads.
The following guidelines are recommended for all layout
designs, but especially strongly for the single-layer PCB
designs. (For example of a 1-layer PCB design, see the 
Application Note AN-6086.) 
General
?   Keep high-current output and power ground paths 
separate from analog input signals and signal
ground paths.
?   For best results, make connections to all pins as 
short and direct as possible.
Power Ground and Analog Ground
?   Power ground (PGND) and analog ground (AGND) 
should meet at one point only.
?   All the control components should be connected to 
AGND without sharing the trace with PGND.
?   The return path for the gate drive current and V
DD
 
capacitor should be connected to the PGND pin.
?   Minimize the ground loops between the driver 
outputs (DRV1, DRV2), MOSFETs, and PGND.
?   Adding the by-pass capacitor for noise on the VDD 
pin is recommended. It should be connected as
close to the pin as possible.  
Gate Drive
?   The gate drive pattern should be wide enough to 
handle 1 A peak current.
?   Keep the controller as close to the MOSFETs as 
possible. This minimizes the length and the loop
area (series inductance) of the high-current gate
drive traces. The gate drive pattern should be as
short as possible to minimize interference.
Current Sensing
?   Current sensing should be as short as possible. 
?   To minimize switching noise, current sensing 
should not make a loop.
Input Voltage Sensing (V
IN
)
?   Since the impedance of voltage divider is large and 
FAN9611 detects the peak of the line voltage, the
VIN pin can be sensitive to the switching noise. The
trace connected to this pin should not cross traces
with high di/dt to minimize the interference.
?   The noise bypass capacitor for V
IN
 should be
connected as close to the pin as possible.
 
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