
SMSC DS – FDC37N958FR
Page 124
Rev. 09/01/99
PARALLEL PORT INTERFACE MULTIPLEXOR
The Parallel Port Physical Interface (PPPI) may
be owned and controlled by any of three
sources. The sources are detailed as follows:
Table 51 - Parallel Port Multiplexing Options
DESCRIPTION
The parallel port physical interface is configured
as a SPP mode bi-directional parallel port
controlled directly by the 8051 through a set of
memory mapped external RAM registers.
The parallel port physical interface is configured
as a standard Floppy Disk Drive interface. All
configuration and control bits pertaining to the
FDC logical device apply to the PPPI in this
mode
The parallel port physical interface is configured
as the legacy parallel port which supports
Compatible, SPP, EPP and ECP modes of
operation. All configuration and control bits
pertaining to the parallel port logical device apply
to the PPPI in this mode.
PPPI
CONTROLLING
SOURCE
DEVICE
8051
CONFIG
REGISTER
0X25
BITS[4:3]
[X:X]
PP_HA
0
FDC
[1:0]
or
[0:1]
1
Host
[0:0]
or
[1:1]
1
When the Host (Parallel Port logical device)
owns/controls the parallel port interface, its state
(i.e., pwrdown) determines the states of the pins.
When
the
FDC
(FDC
owns/controls the Parallel Port interface, its state
(i.e., powerdown) determines the state of the
pins. When the 8051 controls/owns the parallel
port interface, it has direct control of the Parallel
Port Physical Interface pins. Under 8051 control
the Parallel Port Output pins are always enabled
or driven and only tri-state when VCC2 is
removed (powergood=0).
logical
device)
If the Host does not have control of the Parallel
Port Physical Interface (PPPI), then it is left as a
function of the software driver or BIOS to de-
activate the DRQ and IRQ of the Parallel Port
Logical Device by either setting its DMA Channel
Select Configuration Register to 0x04 and its
Interrupt Select Configuration Regsiter to 0x00
or by clearing the Parallel Port Logical Device’s
Activate bit. Also, if the Host does not have
control of the PPPI, then the following parallel
port logical device registers are read as follows.