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參數資料
| 型號： | FDC37N958FR |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Notebook I/O Controller with Enhanced Keyboard and System Control |
| 中文描述： | 筆記本電腦的I / O控制器，具有增強型鍵盤和系統控制 |
| 文件頁數： | 50/316頁 |
| 文件大小： | 999K |
| 代理商： | FDC37N958FR |
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SMSC DS – FDC37N958FR
Page 44
Rev. 09/01/99
Execution Phase
All data transfers to or from the FDC occur during
the execution phase, which can proceed in DMA
or non-DMA mode as indicated in the Specify
command.
After a reset, the FIFO is disabled. Each data
byte is transferred by an FDC IRQ or DRQ
depending on the DMA mode. The Configure
command can enable the FIFO and set the FIFO
threshold value.
The following paragraphs detail the operation of
the FIFO flow control. In these descriptions,
<threshold> is defined as the number of bytes
available to the FDC when service is requested
from the host and ranges from 1 to 16. The
parameter FIFOTHR, which the user programs, is
one less and ranges from 0 to 15.
A low threshold value (i.e. 2) results in longer
periods of time between service requests, but
requires faster servicing of the request for both
read and write cases. The host reads (writes)
from (to) the FIFO until empty (full), then the
transfer request goes inactive. The host must be
very responsive to the service request. This is the
desired case for use with a "fast" system.
A high value of threshold (i.e. 12) is used with a
"sluggish" system by affording a long latency
period after a service request, but results in more
frequent service requests.
Non-DMA Mode - Transfers from the FIFO to the
Host
The FDC’s IRQ pin and RQM bits in the Main
Status Register are activated when the FIFO
contains (16-<threshold>) bytes or the last bytes
of a full sector have been placed in the FIFO. The
FDC’s IRQ pin can be used for interrupt-driven
systems, and RQM can be used for polled
systems. The host must respond to the request
by reading data from the FIFO. This process is
repeated until the last byte is transferred out of the
FIFO. The FDC will deactivate the FDC’s IRQ pin
and RQM bit when the FIFO becomes empty.
Non-DMA Mode - Transfers from the Host to the
FIFO
The FDC’s IRQ pin and RQM bit in the Main
Status Register are activated upon entering the
execution phase of data transfer commands. The
host must respond to the request by writing data
into the FIFO. The FDC’s IRQ pin and RQM bit
remain true until the FIFO becomes full. They are
set true again when the FIFO has <threshold>
bytes remaining in the FIFO. The FDC’s IRQ pin
will also be deactivated if TC and nDACK both go
inactive. The FDC enters the result phase after
the last byte is taken by the FDC from the FIFO
(i.e. FIFO empty condition).
DMA Mode - Transfers from the FIFO to the Host
The FDC activates the FDC’s DRQ pin when the
FIFO contains (16 - <threshold>) bytes, or the last
byte of a full sector transfer has been placed in
the FIFO. The DMA controller must respond to
the request by reading data from the FIFO. The
FDC will deactivate the FDC’s DRQ pin when the
FIFO becomes empty. FDC’s DRQ goes inactive
after nDACK goes active for the last byte of a data
transfer (or on the active edge of nIOR, on the last
byte, if no edge is present on nDACK). A data
underrun may occur if the FDC’s DRQ is not
removed in time to prevent an unwanted cycle.
DMA Mode - Transfers from the Host to the FIFO
The FDC activates the FDC’s DRQ pin when
entering the execution phase of the data transfer
commands. The DMA controller must respond by
activating the nDACK and nIOW pins placing data
in the FIFO. The FDC’s DRQ remains active until
the FIFO becomes full. The FDC’s DRQ is again
set true when the FIFO has <threshold> bytes
remaining in the FIFO. The FDC will also
deactivate the FDC’s DRQ pin when TC becomes
true (qualified by nDACK), indicating that no more
data is required. The FDC’s DRQ goes inactive
after nDACK goes active for the last byte of a data
transfer (or on the active edge of nIOW of the last
byte, if no edge is present on nDACK). A data
overrun may occur if the FDC’s DRQ is not
removed in time to prevent an unwanted cycle.
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