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參數資料
| 型號： | FDP603AL |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | JFETs |
| 英文描述： | N-Channel Logic Level Enhancement Mode Field Effect Transistor(N溝道邏輯電平增強型MOS場效應管) |
| 中文描述： | 33 A, 30 V, 0.022 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-220AB |
| 封裝： | TO-220, 3 PIN |
| 文件頁數： | 1/4頁 |
| 文件大小： | 414K |
| 代理商： | FDP603AL |
April 1998
FDP603AL / FDB603AL
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
_________________________________________________________________________________
Absolute Maximum Ratings
T
C
= 25°C unless otherwise noted
Symbol
Parameter
FDP603AL
FDB603AL
Units
V
DSS
V
GSS
Drain-Source Voltage
30
V
Gate-Source Voltage - Continuous
±20
V
I
D
Drain Current
- Continuous
33
A
- Pulsed
(Note 1)
100
P
D
Total Power Dissipation @ T
C
= 25
°
C
Derate above 25
°
C
50
W
0.33
W/
°
C
T
J
,T
STG
T
L
Operating and Storage Temperature Range
-65 to 175
°C
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
275
°C
THERMAL CHARACTERISTICS
R
θ
JC
R
θ
JA
Thermal Resistance, Junction-to-Case
3
°
C/W
Thermal Resistance, Junction-to-Ambient
62.5
°
C/W
FDP603AL Rev.D
33 A, 30 V. R
DS(ON)
= 0.022
@ V
GS
=10 V
R
DS(ON)
= 0.036
@ V
GS
=4.5 V
.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
High density cell design for extremely low R
DS(ON)
.
175°C maximum junction temperature rating.
These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state
resistance. These devices are particularly suited for low
voltage applications such as DC/DC converters and high
efficiency switching circuits where fast switching, low in-line
power loss, and resistance to transients are needed.
S
D
G
1998 Fairchild Semiconductor Corporation
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