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參數(shù)資料
| 型號： | FDS4897C |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 小信號晶體管 |
| 英文描述： | Dual N & P-Channel PowerTrench MOSFET |
| 中文描述： | 6200 mA, 40 V, 2 CHANNEL, N AND P-CHANNEL, Si, SMALL SIGNAL, MOSFET |
| 封裝： | ROHS COMPLIANT, SO-8 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大小： | 164K |
| 代理商： | FDS4897C |
FDS4897C Rev C(W)
www.fairchildsemi.com
Electrical Characteristics
(continued)
Symbol
Switching Characteristics
(Note 2)
t
d(on)
Turn-On Delay Time
t
r
Turn-On Rise Time
t
d(off)
Turn-Off Delay Time
t
f
Turn-Off Fall Time
Q
g
Total Gate Charge
Q
gs
Gate-Source Charge
Q
gd
Gate-Drain Charge
Drain–Source Diode Characteristics
V
SD
Drain-Source Diode Forward
Voltage
t
rr
Diode Reverse Recovery
Time
Q
rr
Diode Reverse Recovery
Charge
T
A
= 25°C unless otherwise noted
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
9
12
5
15
23
45
3
18
14
20
2.4
3
2.8
4
18
22
10
27
37
72
6
32
20
28
ns
ns
ns
ns
nC
nC
nC
Q1
V
DD
= 20 V, I
D
= 1 A,
V
GS
= 10V, R
GEN
= 6
Ω
Q2
V
DD
= –20 V, I
D
= –1 A,
V
GS
= –10V, R
GEN
= 6
Ω
Q1
V
DS
= 20 V, I
D
= 6.2 A, V
GS
= 10 V
Q2
V
DS
= –20 V, I
D
= –4.4 A,V
GS
=–10 V
V
GS
= 0 V, I
S
= 1.3 A
V
GS
= 0 V, I
S
= –1.3 A
Q1
I
= 6.2 A, d
iF
/d
t
= 100 A/μs
Q2
I
F
= –4.4 A, d
iF
/d
t
= 100 A/μs
(Note 2)
(Note 2)
Q1
Q2
Q1
Q2
Q1
Q2
0.7
–0.7
17
24
7
12
1.2
–1.2
V
ns
nC
Notes:
1.
R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R
θ
JC
is guaranteed by design while R
θ
CA
is determined by the user's board design.
a) 78°C/W when
mounted on a
0.5 in
2
pad of 2 oz
copper
b) 125°C/W when
mounted on a .02 in
2
pad of 2 oz copper
c) 135°C/W when mounted on a
minimum pad.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300
μ
s, Duty Cycle < 2.0%
3. BV(avalanche) Single-Pulse rating is guaranteed by design if device is operated within the UIS SOA boundary of the device.
F
M
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