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參數資料
型號： FMS7401LEN
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： Digital Power Controller
中文描述： 8-BIT, EEPROM, 2.04 MHz, MICROCONTROLLER, PDIP8
封裝： PLASTIC, DIP-8
文件頁數： 33/80頁
文件大小： 1535K
代理商： FMS7401LEN
PRODUCT SPECIFICATION
FMS7401/7401L
REV. 1.0.2 6/23/04
33
Bit 4 of the PSCALE register is the frequency selection (FSEL) bit for the Timer 1 circuit. FSEL is used to select between the
slow or high frequency options, ultimately selecting the F
T1CLK
to be sourced either by the F
ICLK
or F
PWMCLK
(see
Table 13
).
If FSEL=0, the slow frequency option is selected and the F
ICLK
will then source the F
T1CLK
with either a 1/8MHz frequency
determined by the FMODE bit, as discussed later in the section. If FSEL=1, the high frequency option is selected and the
F
PWMCLK
will then source the F
T1CLK
at a frequency selected by the FS[1:0] bits. The FSEL bit may not be set if the PLL is not
enabled (PLLEN=0) or changed while the Timer 1 circuit is in run mode. Any attempts to write to FSEL under this condition
will be ignored and its value will remain unchanged.
Bit 3 (FMODE) of the PSCALE register is the frequency selection bit for the main instruction clock (F
ICLK
). FMODE is used
to select between the slow or high frequency options, ultimately selecting the F
ICLK
to be sourced either by the internal oscilla-
tor (or the external digital clock) operating at F
OSC
2
or the PLL’s F
(FS=0)
output signal.
3
If FMODE=0, the slow frequency
option is selected and the internal oscillator will then source the F
ICLK
at a F
OSC
/2 frequency. If FMODE=1, the high frequency
option is selected and the F
(FS=0)
will then source the F
ICLK
with PLL’s divide-by-8 output frequency. With the FMODE bit
enabled, it is possible to execute instructions at a speed approximately eight times faster than the standard. The FMODE bit
may not be set if the PLL is not enabled (PLLEN=0). Any attempts to write to FMODE while PLLEN=0 will force FMODE=0
ignoring any set instructions. Once the PLL has been enabled, software may change F
ICLK
’s clock source on-the-fly during
normal instruction execution in order to speed-up a particular action.
Bits 2-0 of the PSCALE register are the three prescaler (PS[2:0]) bits used to divide the F
T1CLK
to obtain a wider frequency
range on the PWM output signals (see
Table 14
). The PS bits are used by the Timer 1 circuit to increment the 12-bit TMR1 at a
frequency equal to F
T1CLK
divided-by 1 through 8. The PS bits (like FS) may be changed by software at any time; however, if
the Timer 1 circuit is in run mode, the PS value will not change the prescale division factor until after the TMR1 counter over-
flows ending the current PWM cycle. The last PS value at the TMR1 counter overflow will dictate the prescale divide factor of
the F
T1CLK
for the next PWM cycle. When reading PS, the value reported will be the last value written by software and may not
necessarily reflect the divide factor for the current PWM cycle.
Table 12. Prescale (PSCALE) Register Bit Definitions
Table 13. PLL Divide Factor Selection Bits and the F
T1CLK
Resolution (F
OSC
=2 MHz)
PSCALE Register (addr. 0xA4)
Bit 7
PLLEN
Bit 6
Bit 5
Bit 4
FSEL
Bit 3
FMODE
Bit 2
Bit 1
PS[2:0]
Bit 0
FS[1:0]
Bit
PLLEN
Description
(0) Disables the PLL circuit.
(1) Enables the PLL circuit.
PLL Divide Factor Selection Bits. Refer to
Table 13
for details.
(0) Selects F
ICLK
as Timer 1’s clock (F
T1CLK
) source.
(1) Selects F
PWMCLK
PLL output as Timer 1’s clock (F
T1CLK
) source.
(0) Selects F
CLK
divided-by-2 output as the main system instruction clock (F
ICLK
) source.
(1) Selects F
(FS=0)
PLL output as the main system instruction clock (F
ICLK
) source.
Timer 1 Prescale Selection Bits. Refer to
Table 13
for details.
FS[1:0]
FSEL
FMODE
PS[2:0]
FS[1:0]
0
0
1
1
F
PWMCLK
8 MHz
16 MHz
32 MHz
64 MHz
F
T1CLK
(FSEL=0)
F
T1CLK
(FSEL=1)
8 MHz
16 MHz
32 MHz
64 MHz
Max PWM Freq.
(8-bit resolution)
FSEL=0
FMODE=0
3.906 kHz
3.906 kHz
3.906 kHz
3.906 kHz
Max PWM Freq.
(12-bit resolution)
FSEL=0
FMODE=0
244.14 Hz
244.14 Hz
244.14 Hz
244.14 Hz
FMODE=0
1 MHz
1 MHz
1 MHz
1 MHz
FMODE=1
8 MHz
8 MHz
8 MHz
8 MHz
FSEL=1
31.25 kHz
62.5 kHz
125 kHz
250 kHz
FSEL=1
1.95 kHz
3.9 kHz
7.8 kHz
15.625 kHz
0
1
0
1
相關PDF資料
PDF描述
FMS7401LEN14 Digital Power Controller
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FMS7401LVN14 Digital Power Controller
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相關代理商/技術參數
參數描述
FMS7401LEN14 功能描述:處理器 - 專門應用 Int Controller for Ballast RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數據總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數據緩存: 數據 RAM 大小:128 KB 數據 ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432
FMS7401LEN14_Q 功能描述:處理器 - 專門應用 Int Controller for Ballast RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數據總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數據緩存: 數據 RAM 大小:128 KB 數據 ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432
FMS7401LVN 功能描述:處理器 - 專門應用 Int Controller for Ballast RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數據總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數據緩存: 數據 RAM 大小:128 KB 數據 ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432
FMS7401LVN14 功能描述:8位微控制器 -MCU Int Controller for Ballast RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
FMS7401LVN14_Q 功能描述:8位微控制器 -MCU Int Controller for Ballast RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
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