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參數資料
| 型號： | FS6054 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LOW-SKEW CLOCK FANOUT BUFFER ICs |
| 中文描述： | 低偏移時鐘扇出緩沖器集成電路 |
| 文件頁數： | 2/19頁 |
| 文件大小： | 386K |
| 代理商： | FS6054 |
XT
April 1999
4.5.99
2
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Table 1: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN (FS6050)
PIN (FS6051)
PIN (FS6053)
PIN (FS6054)
TYPE
NAME
DESCRIPTION
11
25
24
4
5
8
9
13
14
17
18
31
32
35
36
40
41
44
45
21
28
38
9
9
9
DI
DI
U
DI
U
O
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DI
U
CLK_IN
SCL
SDA
SDRAM_0
SDRAM_1
SDRAM_2
SDRAM_3
SDRAM_4
SDRAM_5
SDRAM_6
SDRAM_7
SDRAM_8
SDRAM_9
SDRAM_10
SDRAM_11
SDRAM_12
SDRAM_13
SDRAM_14
SDRAM_15
SDRAM_16
SDRAM_17
OE
Clock input for SDRAM clock outputs
Serial clock input
Serial data input/output
15
14
2
3
6
7
-
-
-
-
-
-
-
-
22
23
26
27
11
18
20
15
14
2
3
6
7
-
-
10
11
18
19
-
-
22
23
26
27
12
-
-
15
14
2
3
6
7
-
-
10
11
18
19
-
-
22
23
26
27
12
17
20
SDRAM clock outputs (Byte 0)
SDRAM clock outputs (Byte 1)
SDRAM feedback clock outputs (Byte 2)
Output enable tristates all clock outputs when low
3, 7, 12, 16,
20, 29, 33, 37,
42, 46
23
6, 10, 15, 19,
22, 27, 30, 34,
39, 43
26
1, 2, 47, 48
1, 5, 10, 19,
24, 28
1, 5, 20, 24,
28
1, 5, 24, 28
P
VDD
3.3V ± 5% power supply for SDRAM clock buffers
13
13
13
P
VDD_I
2
C
3.3V ± 5% power supply for serial communications
4, 8, 12, 17,
21, 25
4, 8, 17, 21,
25
4, 8, 21, 25
P
VSS
Ground for SDRAM clock buffers
16
-
16
-
16
-
P
-
VSS_I
2
C
(reserved)
Ground for serial communications
Reserved
Figure 4: Pin Configuration (FS6053)
1
2
3
4
5
6
7
8
V
S
S
V
V
S
V
S
S
V
9
1
1
1
1
1
1
1
S
V
C
S
1
1
1
2
2
2
2
S
S
V
2
C
S
V
S
S
V
V
2
2
2
V
2
C
V
S
2
S
2
S
FS6053
Figure 5: Pin Configuration (FS6054)
1
2
3
4
5
6
7
8
V
S
S
V
V
S
V
S
S
V
9
1
1
1
1
1
1
1
S
V
C
S
1
1
1
2
2
2
2
S
S
V
2
C
S
O
S
S
V
V
2
2
2
V
2
C
S
S
2
S
2
S
FS6054
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