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參數資料
| 型號： | FS6054 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LOW-SKEW CLOCK FANOUT BUFFER ICs |
| 中文描述： | 低偏移時鐘扇出緩沖器集成電路 |
| 文件頁數： | 3/19頁 |
| 文件大小： | 386K |
| 代理商： | FS6054 |
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April 1999
4.5.99
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3.0 Programming Information
Table 2: Clock Enable
CONTROL INPUTS
CLOCK OUTPUTS (MHz)
OE
SDRAM_0:17
0
tristate
1
CLK_IN
3.1
All outputs are enabled and active upon power-up, and all
output control register bits are initialized to one.
The outputs must be configured at power-up and are not
expected to be configured during normal operation. Inac-
tive outputs are held low and are disabled from switching.
Power-Up Initialization
3.1.1
Outputs that are not used in versions of this device with a
reduced pinout are still operational internally. To reduce
power dissipation and crosstalk effects from the unloaded
outputs, it is recommended that these outputs be shut off
via the Control Registers.
Unused Outputs
3.2
A logic-one written to a valid bit location turns on the as-
signed output clock. Likewise, a logic-zero written to a
valid bit location turns off the assigned output clock.
Any unused or reserved register bits should be cleared to
zero.
Serial bits are written to this device in the order shown in
Table 3.
Register Programming
Table 3: Register Summary
SERIAL BIT
DATA BYTE
CLOCK OUTPUT
0
1
2
3
4
5
6
7
8
9
(MSB)
SDRAM_7
SDRAM_6
SDRAM_5
SDRAM_4
SDRAM_3
SDRAM_2
SDRAM_1
SDRAM_0
SDRAM_15
SDRAM_14
SDRAM_13
SDRAM_12
Byte 0
SDRAM Control Register 0
(LSB)
(MSB)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
SDRAM_11
SDRAM_10
SDRAM_9
SDRAM_8
SDRAM_17
SDRAM_16
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 1
SDRAM Control Register 1
(LSB)
(MSB)
Byte 2
SDRAM Control Register 2
(LSB)
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