欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

您現在的位置：買賣IC網 > PDF目錄385317 > GS816272CGC-30I (GSI TECHNOLOGY) 256K x 72 18Mb S/DCD Sync Burst SRAMs PDF資料下載

參數資料

GS816272CC-333/300/250/200/150

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.01 2/2005

25/31

2004, GSI Technology

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.

Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output

drivers on the falling edge of TCK when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-

tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-

ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR

state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-

ated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and

places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction

loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-

Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR

state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

相關PDF資料	PDF描述
GS816272CGC-333	256K x 72 18Mb S/DCD Sync Burst SRAMs
GS816272CGC-333I	256K x 72 18Mb S/DCD Sync Burst SRAMs
GS816272C	256K x 72 18Mb Sync Burst SRAMs
GS8170LW72C-333I	18Mb sigma 1x1Lp CMOS I/O Late Write SigmaRAM
GS8170LW36C-333I	18Mb sigma 1x1Lp CMOS I/O Late Write SigmaRAM

相關代理商/技術參數	參數描述
GS816273C-133	制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 18MBIT 256KX72 3.5NS 209FBGA - Trays
GS816273C-133I	制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 18MBIT 256KX72 3.5NS 209FBGA - Trays
GS816273C-150	制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 18MBIT 256KX72 3.3NS 209FBGA - Trays
GS816273C-150I	制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 18MBIT 256KX72 3.3NS 209FBGA - Trays
GS816273C-166	制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 18MBIT 256KX72 2.9NS 209FBGA - Trays

發布緊急采購，3分鐘左右您將得到回復。

(若只采購一條型號，填寫一行即可)

*型號	*數量	廠商	批號	封裝

添加更多采購