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參數資料

First Write

First Read

Burst Write

Burst Read

Deselect

Notes:

The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.

Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.

Preliminary

GS864418/36E-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.05 6/2006

10/32

2003, GSI Technology

Simplified State Diagram with G

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GS8644ZV72C-200I	72Mb Pipelined and Flow Through Synchronous NBT SRAM
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相關代理商/技術參數	參數描述
GS864418E-250IV	制造商:GSI 制造商全稱:GSI Technology 功能描述:4M x 18, 2M x 36 72Mb S/DCD Sync Burst SRAMs
GS864418E-V	制造商:GSI 制造商全稱:GSI Technology 功能描述:4M x 18, 2M x 36 72Mb S/DCD Sync Burst SRAMs
GS864418GB-200	制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 72MBIT 4MX18 6.5NS/3NS 119FBGA - Trays
GS864418GB-200I	制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 72MBIT 4MX18 6.5NS/3NS 119FBGA - Trays
GS864418GB-200IV	制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 72MBIT 4MX18 6.5NS/3NS 119FPBGA - Trays

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