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參數資料
| 型號： | GS864418E-250I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 4M x 18, 2M x 36 72Mb S/DCD Sync Burst SRAMs |
| 中文描述： | 4M X 18 CACHE SRAM, 6.5 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, FPBGA-165 |
| 文件頁數： | 22/32頁 |
| 文件大小： | 811K |
| 代理商： | GS864418E-250I |
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Instruction Register
ID Code Register
·
31 30 29
Boundary Scan Register
0
1
2
0
· · ·
1
2
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
1
·
1
0
·
·
·
·
·
·
·
·
·
Control Signals
·
Preliminary
GS864418/36E-xxxV
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 6/2006
22/32
2003, GSI Technology
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Not Used
GSI Technology
JEDEC Vendor
ID Code
P
0
1
Bit #
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0 1 1 0 1 1 0 0 1
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相關代理商/技術參數 |
參數描述 |
|---|---|
| GS864418E-250IV | 制造商:GSI 制造商全稱:GSI Technology 功能描述:4M x 18, 2M x 36 72Mb S/DCD Sync Burst SRAMs |
| GS864418E-V | 制造商:GSI 制造商全稱:GSI Technology 功能描述:4M x 18, 2M x 36 72Mb S/DCD Sync Burst SRAMs |
| GS864418GB-200 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 72MBIT 4MX18 6.5NS/3NS 119FBGA - Trays |
| GS864418GB-200I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 72MBIT 4MX18 6.5NS/3NS 119FBGA - Trays |
| GS864418GB-200IV | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 72MBIT 4MX18 6.5NS/3NS 119FPBGA - Trays |
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