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參數資料
| 型號： | GS881Z18T-80I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 8Mb Pipelined and Flow Through Synchronous NBT SRAMs |
| 中文描述： | 512K X 18 ZBT SRAM, 14 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數： | 8/34頁 |
| 文件大?。?/td> | 542K |
| 代理商： | GS881Z18T-80I |
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Rev: 1.10 8/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
8/34
1998, Giga Semconductor, Inc.
Preliminary
.
GS881Z18/36T-11/100/80/66
Synchronous Truth Table
Operation
Type Address E
1
E
2
E
3
ZZ ADV W Bx G CKE CK
DQ
Notes
Deselect Cycle, Power Down
D
None
H
X
X
L
L
X
X
X
L
L-H
High-Z
Deselect Cycle, Power Down
D
None
X
X
H
L
L
X
X
X
L
L-H
High-Z
Deselect Cycle, Power Down
D
None
X
L
X
L
L
X
X
X
L
L-H
High-Z
Deselect Cycle, Continue
D
None
X
X
X
L
H
X
X
X
L
L-H
High-Z
1
Read Cycle, Begin Burst
R
External
L
H
L
L
L
H
X
L
L
L-H
Q
Read Cycle, Continue Burst
B
Next
X
X
X
L
H
X
X
L
L
L-H
Q
1,10
NOP/Read, Begin Burst
R
External
L
H
L
L
L
H
X
H
L
L-H
High-Z
2
Dummy Read, Continue Burst
B
Next
X
X
X
L
H
X
X
H
L
L-H
High-Z
1,2,10
Write Cycle, Begin Burst
W
External
L
H
L
L
L
L
L
X
L
L-H
D
3
Write Cycle, Continue Burst
B
Next
X
X
X
L
H
X
L
X
L
L-H
D
1,3,10
NOP/Write Abort, Begin Burst
W
None
L
H
L
L
L
L
H
X
L
L-H
High-Z
2,3
Write Abort, Continue Burst
B
Next
X
X
X
L
H
X
H
X
L
L-H
High-Z 1,2,3,10
Clock Edge Ignore, Stall
Current
X
X
X
L
X
X
X
X
H
L-H
-
4
Sleep Mode
None
X
X
X
H
X
X
X
X
X
X
High-Z
Notes:
1.
Continue Burst cycles, whether read or write, use the same control inputs; a Deselect continue cycle can only be entered into if a Deselect
cycle is executed first
Dummy read and write abort can be considered NOPs because the SRAMperforms no operation. A Write abort occurs when the W pin is
sampled low but no Byte Write pins are active, so no Write operation is performed.
G can be wired low to mnimze the number of control signals provided to the SRAM Output drivers will automatically turn off during Write
cycles.
If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
X = Dont Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals
are Low
All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
Wait states can be inserted by setting CKE high.
This device contains circuitry that ensures all outputs are in High Z during power-up.
A 2-bit burst counter is incorporated.
10. The address counter is incrimnated for all Burst continue cycles.
2.
3.
4.
5.
6.
7.
8.
9.
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