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參數資料
| 型號： | GS88218BB-V |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs |
| 中文描述： | 為512k × 18，256K × 36 9Mb以上SCD的/雙氰胺同步突發靜態存儲器 |
| 文件頁數： | 27/35頁 |
| 文件大?。?/td> | 863K |
| 代理商： | GS88218BB-V |
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JTAG TAP Instruction Set Summary
Instruction
Code
Description
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
RFU
011
1
SAMPLE/
PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
1
GSI
101
GSI private instruction.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
RFU
110
1
BYPASS
111
Places Bypass Register between TDI and TDO.
1
Notes:
1.
2.
Instruction codes expressed in binary, MSB on left, LSB on right.
Default instruction automatically loaded at power-up and in test-logic-reset state.
GS88218/36B(B/D)-xxxV
Rev: 1.03 6/2006
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
27/35
2002, GSI Technology
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相關代理商/技術參數 |
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| GS88218CB-200 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 9MBIT 512KX18 6.5NS/3NS 119FPBGA - Trays |
| GS88218CB-200I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 9MBIT 512KX18 6.5NS/3NS 119FPBGA - Trays |
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| GS88218CB-250 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 9MBIT 512KX18 5.5NS/2.5NS 119FPBGA - Trays |
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