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參數資料
| 型號： | GS9092A |
| 廠商： | Gennum Corporation |
| 英文描述： | GS9092A GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| 中文描述： | GS9092A GenLINX - R的第三270Mb / s的串行SDI和DVB - ASI在內 |
| 文件頁數： | 7/59頁 |
| 文件大小： | 614K |
| 代理商： | GS9092A |
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GS9092A Data Sheet
34715 - 0
February 2006
7 of 59
12
IOPROC_EN
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal Levels are LVCMOS / LVTTL compatible.
Used to enable or disable the I/O processing features.
When set HIGH, the following I/O processing features of the device are
enabled:
SMPTE 352M Payload Identifier Packet Generation and Insertion
Illegal Code Remapping
EDH Generation and Insertion
Ancillary Data Checksum Insertion
TRS Generation and Insertion
To enable a subset of these features, keep the IOPROC_EN pin HIGH
and disable the individual feature(s) in the IOPROC_DISABLE register
accessible via the host interface.
When this pin is set LOW, the device will enter low-latency mode.
NOTE: When the internal FIFO is configured for video mode or ancillary
data insertion mode, the IOPROC_EN pin must be set HIGH.
13
JTAG/HOST
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Used to select JTAG Test Mode or Host Interface Mode.
When set HIGH, CS_TMS, SCLK_TCK, SDOUT_TDO, and SDIN_TDI
are configured for JTAG boundary scan testing.
When set LOW, CS_TMS, SCLK_TCK, SDOUT_TDO, and SDIN_TDI
are configured as GSPI pins for normal host interface operation.
14
RESET
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Used to reset the internal operating conditions to default setting or to
reset the JTAG test sequence.
Host Mode (JTAG/HOST = LOW):
When asserted LOW, all functional blocks will be set to default
conditions ,SDO and SDO are muted, and all input signals become high
impedance with the exception of the STAT pins which will be driven
LOW.
When set HIGH, normal operation of the device resumes 10usec after
the LOW-to-HIGH transition of the RESET signal.
JTAG Test Mode (JTAG/HOST = HIGH):
When asserted LOW, all functional blocks will be set to default and the
JTAG test sequence will be held in reset.
When set HIGH, normal operation of the JTAG test sequence resumes.
NOTE: For power on reset requirements please see
Device Power Up
on page 55
.
15, 45
CORE_VDD
Non
Synchronous
Input
Power
Power supply for digital logic blocks. Connect to +1.8V DC.
NOTE: For power sequencing requirements please see
Device Power
Up on page 55
.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
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PDF描述 |
|---|---|
| GS9092ACNE3 | GS9092A GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| GS9092 | GS9092 GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| GS9092-CNE3 | GS9092 GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| GSC9620 | P-CHANNEL ENHANCEMENT MODE POWER MOSFET |
| GSD2004S-V-GS08 | DIODE 0.225 A, 300 V, 2 ELEMENT, SILICON, SIGNAL DIODE, TO-236AB, ROHS COMPLIANT, PLASTIC PACKAGE-3, Signal Diode |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS9092A_10 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GenLINX III 270Mb/s Serializer for SDI and DVB-ASI |
| GS9092ACNE3 | 功能描述:RF, RFID, WIRELESS RoHS:是 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:* 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 功能:解串器 數據速率:2.5Gbps 輸入類型:串行 輸出類型:并聯 輸入數:- 輸出數:24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應商設備封裝:64-TQFP-EP（10x10） 包裝:管件 |
| GS9092ACNTE3 | 制造商:Semtech Corporation 功能描述:270Mb/s Transmitter for SDI & ASI |
| GS9092CNE3 | 制造商:Gennum Corporation 功能描述: |
| GS9092-CNE3 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
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