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參數(shù)資料
| 型號： | GT-48001A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Switched Ethernet Controller For 10BaseX(10BaseX交換式快速以太網(wǎng)控制器) |
| 中文描述： | 交換式以太網(wǎng)控制器10BaseX（10BaseX交換式快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 1/101頁 |
| 文件大小： | 1235K |
| 代理商： | GT-48001A |
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GT-48001A
Switched Ethernet Controller
for 10BaseX
Preliminary
Revision 1.6
12/29/97
Please contact Galileo Technology for possible
updates before finalizing a design.
FEATURES
www.galileoT.com
support@galileoT.com
Tel: +1-408.367.1400
Fax: +1-408.367.1401
Single-chip, low cost, Switched Ethernet Controller
- Provides packet switching functions between 8 on-
chip Ethernet ports and the PCI expansion port
- Switch expansion via 1Gbps PCI bus
GalNet Architecture Family Member
- Advanced distributed switching architecture
- Connects seamlessly to other GalNet Family
Devices
- GT-48002A 100BaseX and GT-48003 100VG-
AnyLAN devices available
Incorporates eight 802.3 compliant Ethernet ports
- 10Mbps half-duplex or full-duplex 20Mbps Ethernet
for each port
- Serial mode selectable per port: 10Base-T,
10Base-FL, AUI, and NRZ Synchronous
All digital logic on-chip for each port
- Media Access Control (MAC)
- Manchester encoder/decoder
- Link integrity, Partition
- Automatic polarity detection and correction
- Dual 32-byte FIFOs for receive and transmit
- 7 LEDs for Link Status, Receive, Transmit,
Collision, Forward Unknown Packets, Port Sniffer,
and Half/Full Duplex
- CRC generation for CPU generated packets
High-Performance Distributed Switching Engine
- Performs forwarding and filtering at full wire speed
- 14,880 packets/sec on each Ethernet port
- Flexible software or hardware intervention in
packet routing decisions
Supports ‘Store and Forward’ switching approach
- Low last-bit in to first-bit out delay
- Allows bridging between higher/lower speed
interfaces (Fast Ethernet, ATM, WAN)
Advanced address recognition
- Intelligent address recognition mechanism enables
forwarding rate at full wire speed
- Self-learning mechanism
- Supports up to 8K Unicast addresses and
unlimited Multicast/Broadcast addresses
- Broadcast storm rate filtering
Direct support for packet buffering
- Glueless interface to 1 or 2Mbyte of 60ns EDO
DRAM
- Up to 1K buffers, 1536-bytes each, dynamically
allocated to the receive and PCI ports
PCI Rev 2.1 interface for switch expansion and
management CPU connection
- Up to 10 GT-48001A devices per PCI bus without
PCI-to-PCI bridging
- Up to 32 GalNet devices in a single switch
- Standard CPU connection for management
- Simple interface to other networking interfaces
(ATM, FDDI, etc.)
Extensive network management support
- Repeater MIB and PCI counters
- Address aging support
- Hardware assist for Spanning Tree algorithm
- RMON Station-to-Station connectivity matrix
- CPU access to Address Table
- Ability to define static addresses
- Monitoring (sniffer) mode
HP-EASE Packet sampling management technology
- Takes “snapshots” of packets at programmable
intervals
- Allows for the implementation of HP-EASE or
sampled RMON with low-cost CPUs
208 pin PQFP package
DMA
Transmit
Receive
Collision
Forwarding Unknown
Sniffer
Half/Full Duplex
Status
Switching
Engine
PCI Bus
Data
Address
Control
PCI Bus Controller
Self-Learning &
Address
Recognition
Engine
DRAM
Controller
Frame
Controller
GALNET
Controller
802.3 MAC
Manchester
ENDEC
Tx/Rx
Interface
Port 0
802.3 MAC
Manchester
ENDEC
Tx/Rx
Interface
Port 1
802.3 MAC
Manchester
ENDEC
Tx/Rx
Interface
Port 2
802.3 MAC
Manchester
ENDEC
Tx/Rx
Interface
Port 3
802.3 MAC
Manchester
ENDEC
Tx/Rx
Interface
Port 4
802.3 MAC
Manchester
ENDEC
Tx/Rx
Interface
Port 5
802.3 MAC
Manchester
ENDEC
Tx/Rx
Interface
Port 6
802.3 MAC
Manchester
ENDEC
Tx/Rx
Interface
Port 7
RMON FIFO
Control
PCI Counters
8 x MIB Counters
PCI
Address Table
Statistics Counters
Configuration Registers
Intervention
Mode
Control
Packet Buffers
Serial
Switching
GALNET
Sniffer
Control
Miscellaneous
8 x
LED
Control
Tx
Rx
FIFO FIFO
Tx
Rx
FIFO FIFO
Tx
Rx
FIFO FIFO
Tx
Rx
FIFO FIFO
Tx
Rx
FIFO FIFO
Tx
Rx
FIFO FIFO
Tx
Rx
FIFO FIFO
Tx
Rx
FIFO FIFO
DMA
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