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參數資料
| 型號： | HD74CDC857 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 3.3/2.5-V Phase-lock Loop Clock Driver |
| 中文描述： | 3.3/2.5-V鎖相環時鐘驅動器 |
| 文件頁數： | 1/12頁 |
| 文件大?。?/td> | 54K |
| 代理商： | HD74CDC857 |
HD74CDC857
3.3/2.5-V Phase-lock Loop Clock Driver
ADE-205-222E (Z)
6th. Edition
July 1999
Description
The HD74CDC857 is a high-performance, low-skew, low-jitter, phase locked loop clock driver. It is
specifically designed for use with DDR (Double Data Rate) synchronous DRAMs.
Features
Supports 100 MHz to 150 MHz operation range
*1
Distributes one differential clock input pair to ten differential clock outputs pairs
SSTL_2 (Stub Series Terminated Logic) differential inputs and LVCMOS reset (G) input
Supports spread spectrum clock
External feedback pins (FBIN,
FBIN
) are used to synchronize the outputs to the clock input
Supports both 3.3 V/2.5V analog supply voltage (AV
CC
), and 2.5 V V
DDQ
No external RC network required
Sleep mode detection
48pin TSSOP (Thin Shrink Small Outline Package)
Note: 1. 200 MHz (Max) ver. will be available by 4Q/’99
Function Table
Inputs
:
Outputs
:
PLL
G
CLK
CLK
:
Y
Y
FBOUT
FBOUT
L
L
H
:
Z
Z
Z
Z
:
off
L
H
L
:
Z
Z
Z
Z
:
off
H
L
H
:
L
H
L
H
:
run
H
H
L
:
H
L
H
L
:
run
X
H :
L :
Z :
X :
0 MHz
0 MHz
:
Z
Z
Z
Z
:
off
High level
Low level
High impedance
Don’t care
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