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參數資料
| 型號： | HI7190IP |
| 廠商： | INTERSIL CORP |
| 元件分類： | ADC |
| 英文描述： | null24-Bit, High Precision, Sigma Delta A/D Converter |
| 中文描述： | 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDIP20 |
| 封裝： | PLASTIC, MS-001AD, DIP-20 |
| 文件頁數： | 4/24頁 |
| 文件大小： | 187K |
| 代理商： | HI7190IP |
1874
Input Capacitance, C
IN
V
IN
= 0V
-
5.0
-
pF
DIGITAL OUTPUTS
Output Logic High Voltage, V
OH
I
OUT
= -100
μ
A (Note 7)
2.4
-
-
V
Output Logic Low Voltage, V
OL
I
OUT
= 3mA (Note 7)
-
-
0.4
V
Output Three-State Leakage Current,
I
OZ
V
OUT
= 0V, +5V (Note 7)
-10
1
10
μ
A
Digital Output Capacitance, C
OUT
-
10
-
pF
TIMING CHARACTERISTICS
SCLK Minimum Cycle Time, t
SCLK
200
-
-
ns
SCLK Minimum Pulse Width, t
SCLKPW
50
-
-
ns
CS to SCLK Precharge Time, t
PRE
50
-
-
ns
DRDY Minimum High Pulse Width
(Notes 2, 7)
500
-
-
ns
Data Setup to SCLK Rising Edge
(Write), t
DSU
50
-
-
ns
Data Hold from SCLK Rising Edge
(Write), t
DHLD
0
-
-
ns
Data Read Access from Instruction
Byte Write, t
ACC
(Note 7)
-
-
40
ns
Read Bit Valid from SCLK Falling Edge,
t
DV
(Note 7)
-
-
40
ns
Last Data Transfer to Data Ready
Inactive, t
DRDY
(Note 7)
-
35
-
ns
RESET Low Pulse Width
(Note 2)
100
-
-
ns
SYNC Low Pulse Width
(Note 2)
100
-
-
ns
Oscillator Clock Frequency
(Note 2)
0.1
-
10
MHz
Output Rise/Fall Time
(Note 2)
-
-
30
ns
Input Rise/Fall Time
(Note 2)
-
-
1
μ
s
POWER SUPPLY CHARACTERISTICS
IAV
DD
-
-
1.5
mA
IAV
SS
-
-
1.5
mA
IDV
DD
SCLK = 4MHz
-
-
3.0
mA
Power Dissipation, Active PD
A
SB = ‘0’
-
15
30
mW
Power Dissipation, Standby PD
S
SB = ‘1’
-
5
-
mW
PSRR
(Note 3)
-
-70
-
dB
NOTES:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
2. Parameter guaranteed by design or characterization, not production tested.
3. Applies to both bipolar and unipolar input ranges.
4. These errors can be removed by re-calibrating at the desired operating temperature.
5. Applies after system calibration.
6. Fully differential input signal source is used.
7. See Load Test Circuit, Figure 10, R1 = 10k
, C
L
= 50pF.
8. 1 LSB = 298nV at 24 bits for a Full Scale Range of 5V.
9. V
REF
= V
RHI
- V
RLO
10. These errors are on the order of the output noise shown in Table 1.
11. All inputs except OSC
1
. The OSC
1
input V
IH
is 3.5V minimum.
Electrical Specifications
AV
DD
= +5V, AV
SS
= -5V, DV
DD
= +5V, V
RHI
= +2.5V, V
RLO
= AGND = 0V, V
CM
= AGND,
PGIA Gain = 1, OSC
IN
= 10MHz, Bipolar Input Range Selected, f
N
= 10Hz
(Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HI7190
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