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參數(shù)資料
| 型號： | HT9580 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | Character Pager Controller |
| 中文描述： | 字符傳呼機控制器 |
| 文件頁數(shù)： | 11/63頁 |
| 文件大小： | 444K |
| 代理商： | HT9580 |
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HT9580
11
April 28, 2000
Preliminary
(0005H). If the RTC counter is enabled, the
RTC counter will start to count. The RTC coun-
ter source clock is the X1-clock, so the X1 clock
setting via by SPF12, SPF13 and SPF14 should
be correct.
In order to guarantee that the system clock has
started and stabilized, the SST (System
Start-up Timer) provides an extra delay of 1024
system clock pulse when the system is powered
up.
1
0
RTC
Select 2Hz as the
RTC
Select 1Hz as the
RTC
The low power oscillator of the pager decoder
input clock should be crystal type. The decoder
subsystem low power oscillator, on the other
hand, is of a crystal type which is designed with
a power on start-up function to reduce the sta-
bilization time of the oscillator. This start-up
function is enabled by bit LPM which is ini-
tially set high at power on reset, and should be
cleared to low so as to enable the low-power os-
cillator function. The oscillator configuration is
runninginthelowpowermode.
The system clock oscillator can be enabled/dis-
abled by the register bit, HALT . The system
clock circuit is powered down, when the bit is
set to high. On the other hand, the system clock
circuit is powered up, when the bit is low. When
this bit is set high, the CPU is also stopped.
When this bit is cleared low, the CPU core re-
turns to its normal operation. After this is set
HIGH by the software, it may also be cleared
low when reset, interrupt (IRQ or NMI), RTC
timeout, and port wake-up conditions are met.
0
1
HALT
System clock
enable
System clock
powered down
The WDT is a 16-bit counter and sourced by the
'
' )
@ 4 @
$
6 3
$
! @ 4 @ 0
,
,
low power oscillator
sub-clock divided by 8. The counter is seg-
mented as a 9-bit prescaler and a 7-bit user pro-
grammable counter. The input clock is first
divided by 512 (9-stage) to get the nominal
time-out period. The output of the 9-bit
pre-scaler can then be divided by a 7-bit pro-
grammable counter to generate the longer
watchdog time-out depending on the user s re-
quirements. The 7-bit programmable counter is
controlled by 3 register bits, WS0~2. The
watchdog timer is enabled/disabled by a control
bit WDTEN. To prevent the overflow of this
watchdog timer, a clear-WDT operation should
be executed before the timer overflows. The
clear-WDT operation is to write any number to
the register, CLRWDT (0002H). When the
watchdog timer overflows (checked by bit 3 of
0006H WDTOVFG ), the program counter is
set to FFFC H and FFFD H to read the program
start vector. The definitions of the control bits
are listed below.
1
0
WDTENwatchdog timer
Disable the
watchdog timer
WDT-TMR (Watchdog timer) register
Address
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
State on
POR
0001H
WDT-TMR
X
X
TMR0_PR1 TMR0_PR0
WDTEN
WS2
WS1
WS0
0000 0011
0002H
CLR WDT
X
X
X
X
X
X
X
X
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