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參數資料
| 型號： | HT9580 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | Character Pager Controller |
| 中文描述： | 字符傳呼機控制器 |
| 文件頁數： | 36/63頁 |
| 文件大小： | 444K |
| 代理商： | HT9580 |
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HT9580
36
April 28, 2000
Preliminary
Thedecodercontroladdress(0019H)containsa
battery low flag (BL), an out of range flag (OR),
decoder standby flag (STB), a decoder software
reset (RES), and a decoder on/off control bit
(ON).Thedatareadyandbatteryfailflagarein
the interrupt flag register (0006H). It not only
records the status information but controls the
operation of the decoder.
If the flag status of the battery fail (BF_FG)
changes from 0 to 1 , the following condi-
tions occur.
The pager controller generates an interrupt
ifthevalueofthedatareadyinterruptis 0 .
The pager controller does not generate any
interrupt and no data is transmitted to it if
thevalueofthedatareadyinterruptis 1 .
On the other hand, if the status of the battery
fail flag (BF_FG) changes from 1 to 0 , the
internal node PA.7 of the pager controller will
supply a wake-up function. After the decoder
asserts the data ready request, the data ready
interrupt is generated and the DR_FG bit (bit
5of0006H)issethigh;thenthedatareadyin-
terrupt subroutine runs to process the call
data on the message buffer and resets the
DR_FG bit low.
The functional bits (ON, RES) and indication
bits ( STB, OR, BL, BF_FG and DR_FG) are
all used to control the status of the decoder
which is operated through the pager control
address as described in the following table.
INT flag register (0006H)
Symbol
Bit
R/W
Description
BF_FG
4
R
Battery fail indication bit
Once the decoder detects that the battery fail condition occurred,
the BF_FG will go high.
DR_FG
5
R/W
Data ready interrupt indication bit
When a valid call is detected, data transfers to the message
buffer. The DR_FG bit goes high when the message is terminated
within46bytes,onebatchisattheendduringthemessagereceiv-
ing or the data buffer is full if the data length is more than 46
bytes. The
C software should read the data on the message
buffer within one POCSAG message codeword (32-bit) time. The
C software has to clear the DR_FG bit low.
Decoder control register (0019H)
Symbol
Bit
R/W
Description
ON
0
R/W
On/Off control bit
This bit selects the ON or STANDBY state of the decoder
0: ON state
1: STANDBY RES
If SPI circuit is enabled, it would be better if this bit is set high to
reduce power consumption.
RES
1
R/W
Resets the decoder core output
The C has to set the RES bit low and then high after the pager
controller is turned on.
The reset status must be released before writing data to the de-
coder configuration RAM.
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