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參數(shù)資料
| 型號： | HT9580 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | Character Pager Controller |
| 中文描述： | 字符傳呼機控制器 |
| 文件頁數(shù)： | 13/63頁 |
| 文件大?。?/td> | 444K |
| 代理商： | HT9580 |
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HT9580
13
April 28, 2000
Preliminary
When BZ-Land BZ-H are all 00H, the tone gen-
erator is disabled and BZ is high. The value of
the frequency divider, ranges from 2
(BZ-L=01H, BZ-H=00H)~65536 (BZ-L=FFH,
BZ-H=FFH). Writing to BZ-L only writes the
data into a low byte buffer, while writing to
BZ-H will write the high byte data and the con-
tents of the low byte buffer into the PFD coun-
ter.
When the buzzer generator is disabled by
clearing the MGEN bit in the configuration
register (0000H), the BZ pin remains at its last
state. If the BZ pin is low, the BZ transistor in
the application circuits is always active. There-
fore it is recommended that both BZ-L and
BZ-Hbeclearedandthatthe MGEN bitinthe
configuration register (0000H) also be cleared,
whenitisdesiredtodisableorstopthebuzzer.
The output of the 16-bit PFD counter is divided
by 2 to generate a BZ output with or without
modulation. For example, if the desired output
of BZ is 1.6kHz with modulation and the fre-
quency source is X1-clock (76.8kHz), then the
value of 16-bit PFD counter is set to BZ-L=17H,
BZ-H=00H and MDUT is set high.
7
> = A ;
' B
> = A ;
( B # $
3
> = A
:
0 3
>
' B
&
)
& ;
& ;
Interrupt registers
Address
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
State on
POR
0005H
INT ctrl
0
0
0
RTCEN
ORMSK
RTCMSK
TM1IMSK
TM0IMSK
0000 1111
0006H
INT flag
0
RTC_FG
DR_FG
BF_FG
WDTOVFG
OR_FG
TM1OVFG
TM0OVFG
0000 0000
There are two interrupts for the HT9580: a
Non-Mask Interrupt (NMI) and a generic inter-
rupt request (IRQ). The data ready interrupt
and battery fail interrupt share the NMI call lo-
cation. Which interrupt occurred can be deter-
mined by checking bit BF_FG and the data
ready interrupt bit DR_FG or SPI complete flag
SPIFG (in SPI-CONFIG register). DR_FG is
the data ready interrupt indication bit. When a
valid call is detected, data begins to transfer.
Either one call is terminated or a message
buffer is full or one batch is over but the mes-
sage is not terminated, the data ready inter-
rupt will occur and DR_FG is set high. The
DR_FG bit should be cleared low by the C soft-
ware after a data ready condition has occurred.
A battery fail condition is triggered by a high to
low transition on pin BAF and will set the bat-
tery fail interrupt request flag BF_FG to logic
high. For details, refer to the POCSAG Decoder
section. The sources for the IRQ are timer 0
overflow, timer 1 overflow, out-of-range status
changes and RTC time out. The four interrupt
sources all could be masked, but the four corre-
sponding interrupt flags will still be set when
the interrupt conditions are met. All the four
flags are readable/writeable. When an inter-
rupt condition is met, a flag will be set. If an in-
terrupt routine is performed, the software
should check which flag is set to high then de-
termine what kind of interrupt source occurred.
The WDTOVFG is the flag for the watchdog
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