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參數資料
| 型號： | HTG2150 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit 320 Pixel LCD Microcontroller |
| 中文描述： | 8位微控制器320像素LCD |
| 文件頁數： | 17/49頁 |
| 文件大小： | 316K |
| 代理商： | HTG2150 |
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HTG2150
17
July 24, 2000
Preliminary
All I/O ports maintain their original status.
The PD flag is set and the TO flag is cleared.
The system can leave the HALT mode by means
of an external reset, an interrupt, an external
falling edge signal on port Aor a WDT overflow.
An external reset causes a device initialization
and the WDT overflow performs a warm reset .
ByexaminingtheTOandPDflags,thereasonfor
chip reset can be determined. The PD flag is
cleared when the system powers up or upon exe-
cuting the CLR WDT instruction and is set when
the HALT instruction is executed. The TO flag is
set if the WDT time-out occurs, and causes a
wake-up that only resets the PC and SP, the oth-
ers maintain their original status.
The port Awake-up and interrupt methods can
be considered as a continuation of normal exe-
cution. Each bit in port A can be independently
selected to wake up the device by mask option.
Awakening from an I/O port stimulus, the pro-
gram will resume execution of the next instruc-
tion. If awakening from an interrupt, two
sequences may happen. If the related interrupt
is disabled or the interrupt is enabled but the
stack is full, the program will resume execution
at the next instruction. If the interrupt is en-
abledandthestackisnotfull,theregularinter-
rupt response takes place.
Once a wake-up event occurs, it takes 1024 t
SYS
(system clock period) to resume normal opera-
tion. In other words, a dummy cycle period will
be inserted after the wake-up. If the wake-up
results from an interrupt acknowledge, the ac-
tual interrupt subroutine will be delayed by one
more cycle. If the wake-up results in the next
instruction execution, this will be executed im-
mediately after a dummy period has finished. If
an interrupt request flag is set to 1 before en-
tering the HALT mode, the wake-up function of
the related interrupt will be disabled.
To minimize power consumption, all I/O pins
should be carefully managed before entering
the HALT status.
Reset
Therearethreewaysinwhicharesetcanoccur:
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
The WDT time-out during HALT is different
from other chip reset conditions, since it can
perform a warm reset
and SP, leaving the other circuits in their origi-
nal state. Some registers remain unchanged
during other reset conditions. Most registers
are reset to the initial condition when the re-
set conditions are met. By examining the PD
and TO flags, the program can distinguish be-
tween different chip resets .
that just resets the PC
TO
PD
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal
operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal
operation
1
1
WDT wake-up HALT
Note: u means unchanged
To guarantee that the system oscillator has
started and stabilized, the SST (System
Start-upTimer)providesanextra-delayof1024
system clock pulses when the system powers up
or awakes from the HALT state.
When a system power-up occurs, the SST delay
is added during the reset period. But when the
reset comes from the RES pin, the SST delay is
disabled. Any wake-up from HALT will enable
the SST delay.
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相關代理商/技術參數 |
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