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參數資料
| 型號： | HTG2150 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit 320 Pixel LCD Microcontroller |
| 中文描述： | 8位微控制器320像素LCD |
| 文件頁數： | 7/49頁 |
| 文件大小： | 316K |
| 代理商： | HTG2150 |
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HTG2150
7
July 24, 2000
Preliminary
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Execution flow
Functional Description
Execution flow
The system clock for the HTG2150 is derived
from an RC oscillator. The system clock is inter-
nally divided into four non-overlapping clocks.
One instruction cycle consists of four system
clock cycles.
Instruction fetching and execution are pipelined in
such a way that a fetch takes one instruction cycle
while decoding and execution takes the next in-
struction cycle. However, the pipelining scheme
causeseachinstructiontoeffectivelyexecuteinone
cycle. If an instruction changes the program coun-
ter,twocyclesarerequiredtocompletetheinstruc-
tion.
Program counter
PC
The 13-bit program counter (PC) controls the
sequenceinwhichtheinstructionsstoredinthe
program ROM are executed and its contents
specify a maximum of 8192 addresses.
After accessing a program memory word to
fetch an instruction code, the contents of the
program counter are incremented by one. The
program counter then points to the memory
word containing the next instruction code.
When executing a jump instruction, conditional
skip execution, loading PCL register, subrou-
tine call, initial reset, internal interrupt, exter-
nal interrupt or return from subroutine, the PC
manipulates the program transfer by loading
the address corresponding to each instruction.
The conditional skip is activated by instruction.
Once the condition is met, the next instruction,
fetched during the current instruction execu-
tion, is discarded and a dummy cycle replaces it
to get the proper instruction. Otherwise pro-
ceed with the next instruction.
The lower byte of the program counter (PCL) is
a readable and writeable register (06H).
Moving data into the PCL performs a short
jump. The destination will be within 256 loca-
tions.
When a control transfer takes place, an addi-
tional dummy cycle is required.
Program memory
ROM
The program memory, which contains execut-
able program instructions, data and table infor-
mation, is composed of a 16384 x 16 bit format.
However as the PC (program counter) is com-
prised of only 13 bits, the remaining 1 ROM ad-
dress bit is managed by dividing the program
memory into 2 banks, each bank having a range
between 0000H and 1FFFH. To move from the
present ROM bank to a different ROM bank,
the higher 1 bit of the ROM address are set by
the BP (Bank Pointer), while the remaining 13
bits of the PC are set in the usual way by exe-
cuting the appropriate jump or call instruction.
As the full 14 address bits are latched during
the execution of a call or jump instruction, the
correct value of the BP must first be setup be-
fore a jump or call is executed. When either a
software or hardware interrupt is received,
note that no matter which ROM bank the pro-
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相關代理商/技術參數 |
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