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參數資料
| 型號： | IS42S32400A-10TL |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | CABLE ASSEMBLY; SMA MALE RIGHT ANGLE TO; SMA FEMALE BULKHEAD; 50 OHM, PE-SR405FL (.085" RE-SHAPABLE); 18" CABLE LENGTH; |
| 中文描述： | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO86 |
| 封裝： | LEAD FREE, PLASTIC, TSOP2-86 |
| 文件頁數： | 32/66頁 |
| 文件大小： | 556K |
| 代理商： | IS42S32400A-10TL |
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ISSI
32
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
ADVANCED INFORMATION
Rev. 00A
06/01/02
IS42S81600A, IS42S16800A, IS42S32400A
IS42LS81600A, IS42LS16800A, IS42LS32400A
CLK
CKE
ROW ADDRESS
BANK ADDRESS
CS
RAS
CAS
WE
A0-A11
BA0, BA1
HIGH
ACTIVATING SPECIFIC ROW WITHIN SPE-
CIFIC BANK
DON'T CARE
CLK
COMMAND
ACTIVE
NOP
NOP
t
RCD
T0
T1
T2
T3
T4
READ or
WRITE
CHIP OPERATION
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued to a
bank within the SDRAM, a row in that bank must be
“opened.”
This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated (see
Activating Specific Row Within Specific Bank
).
After opening a row
(issuing an ACTIVE command)
, a
READ or WRITE command may be issued to that row,
subject to the t
RCD
specification. Minimum t
RCD
should be
divided by the clock period and rounded up to the next whole
number to determine the earliest clock edge after the
ACTIVE command on which a READ or WRITE command
can be entered. For example, a t
RCD
specification of 20ns
with a 125 MHz clock (8ns period) results in 2.5 clocks,
rounded to 3. This is reflected in the following example,
which covers any case where 2 < [t
RCD
(MIN)/t
CK
]
≤
3. (The
same procedure is used to convert other specification limits
from time units to clock cycles).
A subsequent ACTIVE command to a different row in the
same bank can only be issued after the previous active row
has been “closed” (precharged). The minimum time interval
between successive ACTIVE commands to the same bank
is defined by t
RC
.
A subsequent ACTIVE command to another bank can be
issued while the first bank is being accessed, which results
in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to
different banks is defined by t
RRD
.
EXAMPLE: MEETING TRCD (MIN) WHEN 2
<
[TRCD (MIN)/TCK]
≤
3
相關PDF資料 |
PDF描述 |
|---|---|
| IS42S32400A-10TLI | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S16800A | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S16800A-6T | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S16800A-6TL | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S16800A-7T | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| IS42S32400A-10TLI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400A-6T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400A-6TL | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS42S32400A-6T-TR | 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 128M-Bit 4Mx32 3.3V 86-Pin TSOP-II T/R |
| IS42S32400A-7B | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
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