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參數(shù)資料
| 型號： | IS61SF25616-11B |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | SRAM |
| 英文描述： | 256K X 16 CACHE SRAM, 11 ns, PBGA119 |
| 封裝： | PLASTIC, BGA-119 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大小： | 147K |
| 代理商： | IS61SF25616-11B |
This document contains PRELIMINARY INFORMATION. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible
product. We assume no responsibility for any errors which may appear in this publication. Copyright 1999, Integrated Silicon Solution, Inc.
FEATURES
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
Pentium or linear burst sequence control
using MODE input
Three chip enables for simple depth expansion
and address pipelining
Common data inputs and data outputs
JEDEC 100-pin TQFP and
119-pin PBGA package
Single +3.3V, +10%, –5% power supply
3.3V I/O supply
Power-down snooze mode
DESCRIPTION
The
ISSI IS61SF25616 is a high-speed, low-power
synchronous static RAM designed to provide a burstable,
high-performance, secondary cache for the Pentium,
680X0, and PowerPC microprocessors. It is organized
as 262,144 words by 16 bits, fabricated with
ISSI's advanced
CMOS technology. The device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs into
a single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQa, BW2 controls DQb, conditioned by BWE
being LOW. A LOW on
GW input would cause all bytes to be
written.
Bursts can be initiated with either
ADSP (Address Status
Processor) or
ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
by the IS61SF25616 and controlled by the
ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
IS61SF25616
256K x 16 SYNCHRONOUS
FLOW-THROUGH STATIC RAM
PRELIMINARY
MAY1999
FAST ACCESS TIME
Symbol
Parameter
7.5
8
8.5
10
11
Units
tKQ
Clock Access Time
7.5
8
8.5
10
11
ns
tKC
Cycle Time
8.5
10
11
15
20
ns
Frenquency
117
100
90
66
50
MHz
Note:
1. Shaded area = ADVANCE INFORMATION DATA.
ISSI
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
PRELIMINARY SR056-1A
05/24/99
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS61SF25616-8.5TQ | 256K X 16 CACHE SRAM, 8.5 ns, PQFP100 |
| IS61VPD10018-200BI | 1M X 18 CACHE SRAM, 3.1 ns, PBGA119 |
| IS62VV51216LL-70MI | 512K X 16 STANDARD SRAM, 70 ns, PBGA48 |
| IS63LV1024-10K | 128K X 8 STANDARD SRAM, 10 ns, PDSO32 |
| IS63LV1024-8KL | 128K X 8 STANDARD SRAM, 8 ns, PDSO32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS61SF25618-8.5TQI | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 256K x 18 8.5ns 100-Pin TQFP |
| IS61SF25618-8.5TQI-TR | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 256K x 18 8.5ns 100-Pin TQFP T/R |
| IS61SF51218T-10TQ | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Sync Single 3.3V 8M-Bit 512K x 16 10ns 100-Pin TQFP |
| IS61SP12836-133B | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61SP12836-133TQ-T | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Sync Quad 3.3V 4.5M-Bit 128K x 36 4ns 100-Pin TQFP T/R |
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