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參數(shù)資料
型號(hào): ISP1181DGG
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: INDUCTOR 4.7NH +-.3NH 0402 SMD
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PDSO48
封裝: 6.10 MM, PLASTIC, TSSOP-48
文件頁(yè)數(shù): 27/69頁(yè)
文件大小: 1655K
代理商: ISP1181DGG
Philips Semiconductors
ISP1181
Full-speed USB interface
Objective specification
Rev. 01 — 13 March 2000
27 of 69
9397 750 06896
Philips Electronics N.V. 2000. All rights reserved.
Code (Hex): B8/B9 —
write/read Mode Register
Transaction —
write/read 1 byte
[1]
Unchanged by a bus reset.
12.1.4
Write/Read Hardware Configuration
This command is used to access the Hardware Configuration Register, which
consists of 2 bytes. The first (lower) byte contains the device configuration and
control values, the second (upper) byte holds the clock control bits and the clock
division factor. The bit allocation is given in
Table 22
. A bus reset will not change any
of the programmed bit values.
The Hardware Configuration Register controls the connection to the USB bus, clock
activity and power supply during ‘suspend’ state, output clock frequency, DMA
operating mode and pin configurations (polarity, signalling mode).
Code (Hex): BA/BB —
write/read Hardware Configuration Register
Transaction —
write/read 2 bytes
Table 20: Mode Register: bit allocation
Bit
7
Symbol
DMAWD
Reset
0
[1]
Access
R/W
6
5
4
3
2
1
0
SNDRSU
0
R/W
GOSUSP
0
R/W
reserved
0
R/W
INTENA
0
[1]
R/W
DBGMOD
0
[1]
R/W
DISGLBL
0
[1]
R/W
SOFTCT
0
[1]
R/W
Table 21: Mode Register: bit description
Bit
Symbol
7
DMAWD
Description
A logic 1 selects 16-bit DMA bus width (bus configuration modes
0 and 2). A logic 0 selects 8-bit DMA bus width. Bus reset value:
unchanged.
Writing a logic 1 followed by a logic 0 will generate an upstream
‘resume’ signal of 10 ms duration, after a 5 ms delay.
Writing a logic 1 followed by a logic 0 will activate ‘suspend’
mode.
reserved
A logic 1 enables all interrupts. Bus reset value: unchanged.
A logic 1 enables debug mode. where all NAKs and errors will
generate an interrupt. A logic 0 selects normal operation, where
interrupts are generated on every ACK (bulk endpoints) or after
every data transfer (isochronous endpoints). Bus reset value:
unchanged.
A logic 1 disables GoodLInk LED blinking on USB traffic. The
LED will be continuously on (GL = LOW) after successful
enumeration. Bus reset value: unchanged.
A logic 1 enables SoftConnect (see
Section 7.4
). This bit is
ignored if EXTPUL = 1 in the Hardware Configuration Register
(see
Table 22
). Bus reset value: unchanged.
6
SNDRSU
5
GOSUSP
4
3
2
-
INTENA
DBGMOD
1
DISGLBL
0
SOFTCT
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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