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參數資料
| 型號： | L64013A1 |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數： | 14/16頁 |
| 文件大小： | 273K |
| 代理商： | L64013A1 |
L64013 VIP Bridge
7
CH_DATA[7:0] Channel Data Bus
Output
The CH_DATA[7:0] output bus serves as a parallel output
path for channel data.
VREQ_N
Video Transfer Request
Input
The L64020 asserts VREQ_N LOW when it is ready to
receive a new byte of coded video data.
VVALID_N
Video Data Valid
Output
The rising edge of VVALID informs the L64020 to write
the next byte of video data that is present on the
CH_DATA[7:0] data bus.
L64020 Host Interface
CS_N
Chip Select
Output
Assertion of this active-LOW signal indicates an attempt
by an external host CPU to access the L64020 either for
a read or a write bus cycle.
DATA[7:0]
Host Data Bus
Input/Output
Data is transferred on this eight-bit bidirectional host data
bus for data communication between the host CPU and
the L64020 registers, DMA cycles, and PCM FIFO
cycles.
DREQ_N
DMA Transfer Request
Input
The L64020 asserts this active-LOW input when it is
ready to receive a new byte of DMA data.
DVD_ADDRESS[9:0]
Address Bus
Output
This 10-bit address bus is used to access the L64020’s
internal registers.
DVDRESET_N DVD Reset
Output
This signal is an active-LOW reset output controlled by
bit 0 of I/O register 0x298.
PREQ_N
PCM FIFO Request
Input
The L64020 asserts this signal LOW to indicate that its
PCM FIFO is ready to accept data.
L64013VIP Page 7 Friday, May 29, 1998 8:29 AM
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