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參數(shù)資料
| 型號： | L64733C-44 |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC44 |
| 封裝： | 7 X 7 MM, 0.90 MM HEIGHT, QFN-44 |
| 文件頁數(shù)： | 8/52頁 |
| 文件大小： | 552K |
| 代理商： | L64733C-44 |
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16
L64733C/L64734 Tuner and Satellite Receiver Chipset
XOIN
Crystal Oscillator In
Input
The XOIN pin provides a crystal oscillator or external
reference clock input. Normally, a 15 MHz crystal is
connected to the XOIN pin.
XOOUT
Crystal Oscillator Out
Output
The XOOUT pin is the crystal oscillator output pin.
Phase-Locked Loop (PLL) Interface
The internal PLL generates the signals to operate the ADC,
Demodulator, and FEC modules.
LCLK
Decimated Clock Output
Output
The L64734 internal clock generation module generates
the LCLK signal. LCLK is derived from CLK by dividing
by the value of the CLK_DIV2 register parameter.
LP2
Input to VCO
Input
The LP2 signal is the input to the internal
voltage-controlled oscillator. Normally, it is connected to
the output of an external RC lter circuit.
PCLK
PLL Clock Output
Output
The L64734 internal PLL clock synthesis module
generates the PCLK signal. The reference crystal
connected between the XOIN and XOOUT pins drives
the PLL. The PLL clock synthesis module can be
congured to generate a PCLK rate that is appropriate for
all data rates.
PLLAGND
PLL Analog Ground
Input
PLLAGND is the analog ground pin for the PLL module
and normally is connected to the system ground plane.
PLLVDD
PLL Power
Input
PLLVDD is the power supply pin for the PLL module and
normally is connected to the system power (VDD) plane.
PLLVSS
PLL Ground
Input
PLLVSS is the ground pin for the PLL module and
normally is connected to the system ground plane.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| L64734 | 制造商:LSI 制造商全稱:LSI 功能描述:Tuner and Satellite Receiver Chipset |
| L64734C-45 | 制造商:LSI 功能描述: 制造商:LSI Corporation 功能描述: |
| L64735GM-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Image Processor |
| L64735GM-27 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Image Processor |
| L64735GM-35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Image Processor |
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